9831289f6f
S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// OWL pll clock driver
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Author: David Liu <liuwei@actions-semi.com>
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//
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// Copyright (c) 2018 Linaro Ltd.
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// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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#ifndef _OWL_PLL_H_
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#define _OWL_PLL_H_
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#include "owl-common.h"
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#define OWL_PLL_DEF_DELAY 50
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/* last entry should have rate = 0 */
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struct clk_pll_table {
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unsigned int val;
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unsigned long rate;
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};
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struct owl_pll_hw {
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u32 reg;
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u32 bfreq;
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u8 bit_idx;
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u8 shift;
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u8 width;
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u8 min_mul;
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u8 max_mul;
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u8 delay;
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const struct clk_pll_table *table;
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};
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struct owl_pll {
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struct owl_pll_hw pll_hw;
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struct owl_clk_common common;
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};
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#define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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_width, _min_mul, _max_mul, _delay, _table) \
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{ \
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.reg = _reg, \
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.bfreq = _bfreq, \
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.bit_idx = _bit_idx, \
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.shift = _shift, \
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.width = _width, \
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.min_mul = _min_mul, \
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.max_mul = _max_mul, \
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.delay = _delay, \
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.table = _table, \
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}
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#define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \
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_shift, _width, _min_mul, _max_mul, _table, _flags) \
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struct owl_pll _struct = { \
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.pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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_width, _min_mul, _max_mul, \
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OWL_PLL_DEF_DELAY, _table), \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&owl_pll_ops, \
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_flags), \
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}, \
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}
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#define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \
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_shift, _width, _min_mul, _max_mul, _table, _flags) \
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struct owl_pll _struct = { \
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.pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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_width, _min_mul, _max_mul, \
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OWL_PLL_DEF_DELAY, _table), \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT_NO_PARENT(_name, \
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&owl_pll_ops, \
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_flags), \
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}, \
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}
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#define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \
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_shift, _width, _min_mul, _max_mul, _delay, _table, \
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_flags) \
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struct owl_pll _struct = { \
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.pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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_width, _min_mul, _max_mul, \
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_delay, _table), \
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.common = { \
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.regmap = NULL, \
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.hw.init = CLK_HW_INIT_NO_PARENT(_name, \
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&owl_pll_ops, \
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_flags), \
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}, \
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}
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#define mul_mask(m) ((1 << ((m)->width)) - 1)
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static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
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{
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struct owl_clk_common *common = hw_to_owl_clk_common(hw);
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return container_of(common, struct owl_pll, common);
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}
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extern const struct clk_ops owl_pll_ops;
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#endif /* _OWL_PLL_H_ */
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