88df36f2e6
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the 1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level and disabling the "withstand function". H616 supports this capability on its main PIO only. A100 supports this capability on both its PIO and R-PIO. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220713025233.27248-4-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
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*
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* Based on:
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* huangshuosheng <huangshuosheng@allwinnertech.com>
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/platform_device.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin a100_r_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2c1"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2c1"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_pwm"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_cir"), /* IN */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
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};
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static const struct sunxi_pinctrl_desc a100_r_pinctrl_data = {
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.pins = a100_r_pins,
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.npins = ARRAY_SIZE(a100_r_pins),
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.pin_base = PL_BASE,
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.irq_banks = 1,
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.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
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};
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static int a100_r_pinctrl_probe(struct platform_device *pdev)
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{
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return sunxi_pinctrl_init(pdev, &a100_r_pinctrl_data);
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}
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static const struct of_device_id a100_r_pinctrl_match[] = {
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{ .compatible = "allwinner,sun50i-a100-r-pinctrl", },
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{}
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};
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MODULE_DEVICE_TABLE(of, a100_r_pinctrl_match);
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static struct platform_driver a100_r_pinctrl_driver = {
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.probe = a100_r_pinctrl_probe,
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.driver = {
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.name = "sun50iw10p1-r-pinctrl",
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.of_match_table = a100_r_pinctrl_match,
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},
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};
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module_platform_driver(a100_r_pinctrl_driver);
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