35c32e3095
When "Bus" was renamed to "Core" the header underline update was missed.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Fixes: 5f653f7590 ("cxl/core: Rename bus.c to core.c")
Reviewed-by: Vishal Verma <vishal.l.verma@intel.com>
Link: https://lore.kernel.org/r/162154034053.1995075.17047445540000243300.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
47 lines
1.2 KiB
ReStructuredText
47 lines
1.2 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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===================================
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Compute Express Link Memory Devices
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===================================
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A Compute Express Link Memory Device is a CXL component that implements the
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CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
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or both. It is enumerated as a PCI device for configuration and passing
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messages over an MMIO mailbox. Its contribution to the System Physical
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Address space is handled via HDM (Host Managed Device Memory) decoders
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that optionally define a device's contribution to an interleaved address
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range across multiple devices underneath a host-bridge or interleaved
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across host-bridges.
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Driver Infrastructure
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=====================
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This section covers the driver infrastructure for a CXL memory device.
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CXL Memory Device
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-----------------
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.. kernel-doc:: drivers/cxl/mem.c
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:doc: cxl mem
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.. kernel-doc:: drivers/cxl/mem.c
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:internal:
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CXL Core
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--------
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.. kernel-doc:: drivers/cxl/core.c
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:doc: cxl core
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External Interfaces
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===================
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CXL IOCTL Interface
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-------------------
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.. kernel-doc:: include/uapi/linux/cxl_mem.h
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:doc: UAPI
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.. kernel-doc:: include/uapi/linux/cxl_mem.h
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:internal:
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