1883a0a465
GPU saves accumulated context runtime (in CS timestamp units) in PPHWSP which will be useful for us in cases when we are not able to track context busyness ourselves (like with GuC). Keep a copy of this in struct intel_context from where it can be easily read even if the context is not pinned. v2: (Chris) * Do not store pphwsp address in intel_context. * Log CS wrap-around. * Simplify calculation by relying on integer wraparound. v3: * Include total/avg in traces and error state for debugging Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200216133620.394962-1-chris@chris-wilson.co.uk
57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2014-2018 Intel Corporation
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*/
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#ifndef _INTEL_LRC_REG_H_
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#define _INTEL_LRC_REG_H_
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#include <linux/types.h>
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/* GEN8 to GEN11 Reg State Context */
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#define CTX_CONTEXT_CONTROL (0x02 + 1)
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#define CTX_RING_HEAD (0x04 + 1)
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#define CTX_RING_TAIL (0x06 + 1)
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#define CTX_RING_START (0x08 + 1)
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#define CTX_RING_CTL (0x0a + 1)
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#define CTX_BB_STATE (0x10 + 1)
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#define CTX_BB_PER_CTX_PTR (0x18 + 1)
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#define CTX_TIMESTAMP (0x22 + 1)
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#define CTX_PDP3_UDW (0x24 + 1)
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#define CTX_PDP3_LDW (0x26 + 1)
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#define CTX_PDP2_UDW (0x28 + 1)
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#define CTX_PDP2_LDW (0x2a + 1)
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#define CTX_PDP1_UDW (0x2c + 1)
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#define CTX_PDP1_LDW (0x2e + 1)
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#define CTX_PDP0_UDW (0x30 + 1)
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#define CTX_PDP0_LDW (0x32 + 1)
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#define CTX_R_PWR_CLK_STATE (0x42 + 1)
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#define GEN9_CTX_RING_MI_MODE 0x54
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/* GEN12+ Reg State Context */
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#define GEN12_CTX_BB_PER_CTX_PTR (0x12 + 1)
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#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
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u32 *reg_state__ = (reg_state); \
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const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
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(reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \
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(reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \
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} while (0)
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#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
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u32 *reg_state__ = (reg_state); \
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const u64 addr__ = px_dma(ppgtt->pd); \
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(reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \
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(reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \
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} while (0)
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#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
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#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
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#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19
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#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A
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#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD
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#endif /* _INTEL_LRC_REG_H_ */
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