a747371748
All boards based on AR5312/AR2315 SoC have a special structure located at the end of flash. This structure contains board-specific data such as Ethernet and Wireless MAC addresses. The flash is mapped to the memmory at predefined location. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8243/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
74 lines
2.8 KiB
C
74 lines
2.8 KiB
C
#ifndef __ASM_MACH_ATH25_PLATFORM_H
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#define __ASM_MACH_ATH25_PLATFORM_H
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#include <linux/etherdevice.h>
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/*
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* This is board-specific data that is stored in a "fixed" location in flash.
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* It is shared across operating systems, so it should not be changed lightly.
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* The main reason we need it is in order to extract the ethernet MAC
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* address(es).
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*/
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struct ath25_boarddata {
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u32 magic; /* board data is valid */
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#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
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u16 cksum; /* checksum (starting with BD_REV 2) */
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u16 rev; /* revision of this struct */
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#define BD_REV 4
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char board_name[64]; /* Name of board */
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u16 major; /* Board major number */
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u16 minor; /* Board minor number */
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u32 flags; /* Board configuration */
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#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
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#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
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#define BD_UART1 0x00000004 /* UART1 is stuffed */
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#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
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#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
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#define BD_SYSLED 0x00000020 /* System LED stuffed */
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#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
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#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
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#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
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#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
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#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
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#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
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#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
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#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
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#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
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#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
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#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
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#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
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u16 reset_config_gpio; /* Reset factory GPIO pin */
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u16 sys_led_gpio; /* System LED GPIO pin */
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u32 cpu_freq; /* CPU core frequency in Hz */
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u32 sys_freq; /* System frequency in Hz */
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u32 cnt_freq; /* Calculated C0_COUNT frequency */
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u8 wlan0_mac[ETH_ALEN];
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u8 enet0_mac[ETH_ALEN];
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u8 enet1_mac[ETH_ALEN];
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u16 pci_id; /* Pseudo PCIID for common code */
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u16 mem_cap; /* cap bank1 in MB */
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/* version 3 */
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u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
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};
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#define BOARD_CONFIG_BUFSZ 0x1000
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/*
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* Platform device information for the Wireless MAC
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*/
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struct ar231x_board_config {
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u16 devid;
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/* board config data */
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struct ath25_boarddata *config;
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/* radio calibration data */
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const char *radio;
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};
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#endif /* __ASM_MACH_ATH25_PLATFORM_H */
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