a83fe6b6ad
This patch adds multi-TC support. PTP is automatically disabled when the user enables more than 2 TCs, otherwise traffic on TC2 won't quite work, because it's reserved for PTP. Signed-off-by: Dmitry Bezrukov <dbezrukov@marvell.com> Co-developed-by: Dmitry Bogdanov <dbogdanov@marvell.com> Signed-off-by: Dmitry Bogdanov <dbogdanov@marvell.com> Co-developed-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* aQuantia Corporation Network Driver
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* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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*/
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/* File aq_hw_utils.h: Declaration of helper functions used across hardware
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* layer.
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*/
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#ifndef AQ_HW_UTILS_H
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#define AQ_HW_UTILS_H
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#include <linux/iopoll.h>
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#include "aq_common.h"
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#ifndef HIDWORD
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#define LODWORD(_qw) ((u32)(_qw))
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#define HIDWORD(_qw) ((u32)(((_qw) >> 32) & 0xffffffff))
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#endif
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#define AQ_HW_SLEEP(_US_) mdelay(_US_)
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#define aq_pr_err(...) pr_err(AQ_CFG_DRV_NAME ": " __VA_ARGS__)
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#define aq_pr_trace(...) pr_info(AQ_CFG_DRV_NAME ": " __VA_ARGS__)
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struct aq_hw_s;
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void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
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u32 shift, u32 val);
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u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift);
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u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg);
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void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value);
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u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg);
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int aq_hw_err_from_flags(struct aq_hw_s *hw);
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int aq_hw_num_tcs(struct aq_hw_s *hw);
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int aq_hw_q_per_tc(struct aq_hw_s *hw);
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#endif /* AQ_HW_UTILS_H */
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