da9803dfd3
called SEV by also encrypting the guest register state, making the registers inaccessible to the hypervisor by en-/decrypting them on world switches. Thus, it adds additional protection to Linux guests against exfiltration, control flow and rollback attacks. With SEV-ES, the guest is in full control of what registers the hypervisor can access. This is provided by a guest-host exchange mechanism based on a new exception vector called VMM Communication Exception (#VC), a new instruction called VMGEXIT and a shared Guest-Host Communication Block which is a decrypted page shared between the guest and the hypervisor. Intercepts to the hypervisor become #VC exceptions in an SEV-ES guest so in order for that exception mechanism to work, the early x86 init code needed to be made able to handle exceptions, which, in itself, brings a bunch of very nice cleanups and improvements to the early boot code like an early page fault handler, allowing for on-demand building of the identity mapping. With that, !KASLR configurations do not use the EFI page table anymore but switch to a kernel-controlled one. The main part of this series adds the support for that new exchange mechanism. The goal has been to keep this as much as possibly separate from the core x86 code by concentrating the machinery in two SEV-ES-specific files: arch/x86/kernel/sev-es-shared.c arch/x86/kernel/sev-es.c Other interaction with core x86 code has been kept at minimum and behind static keys to minimize the performance impact on !SEV-ES setups. Work by Joerg Roedel and Thomas Lendacky and others. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAl+FiKYACgkQEsHwGGHe VUqS5BAAlh5mKwtxXMyFyAIHa5tpsgDjbecFzy1UVmZyxN0JHLlM3NLmb+K52drY PiWjNNMi/cFMFazkuLFHuY0poBWrZml8zRS/mExKgUJC6EtguS9FQnRE9xjDBoWQ gOTSGJWEzT5wnFqo8qHwlC2CDCSF1hfL8ks3cUFW2tCWus4F9pyaMSGfFqD224rg Lh/8+arDMSIKE4uH0cm7iSuyNpbobId0l5JNDfCEFDYRigQZ6pZsQ9pbmbEpncs4 rmjDvBA5eHDlNMXq0ukqyrjxWTX4ZLBOBvuLhpyssSXnnu2T+Tcxg09+ZSTyJAe0 LyC9Wfo0v78JASXMAdeH9b1d1mRYNMqjvnBItNQoqweoqUXWz7kvgxCOp6b/G4xp cX5YhB6BprBW2DXL45frMRT/zX77UkEKYc5+0IBegV2xfnhRsjqQAQaWLIksyEaX nz9/C6+1Sr2IAv271yykeJtY6gtlRjg/usTlYpev+K0ghvGvTmuilEiTltjHrso1 XAMbfWHQGSd61LNXofvx/GLNfGBisS6dHVHwtkayinSjXNdWxI6w9fhbWVjQ+y2V hOF05lmzaJSG5kPLrsFHFqm2YcxOmsWkYYDBHvtmBkMZSf5B+9xxDv97Uy9NETcr eSYk//TEkKQqVazfCQS/9LSm0MllqKbwNO25sl0Tw2k6PnheO2g= =toqi -----END PGP SIGNATURE----- Merge tag 'x86_seves_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 SEV-ES support from Borislav Petkov: "SEV-ES enhances the current guest memory encryption support called SEV by also encrypting the guest register state, making the registers inaccessible to the hypervisor by en-/decrypting them on world switches. Thus, it adds additional protection to Linux guests against exfiltration, control flow and rollback attacks. With SEV-ES, the guest is in full control of what registers the hypervisor can access. This is provided by a guest-host exchange mechanism based on a new exception vector called VMM Communication Exception (#VC), a new instruction called VMGEXIT and a shared Guest-Host Communication Block which is a decrypted page shared between the guest and the hypervisor. Intercepts to the hypervisor become #VC exceptions in an SEV-ES guest so in order for that exception mechanism to work, the early x86 init code needed to be made able to handle exceptions, which, in itself, brings a bunch of very nice cleanups and improvements to the early boot code like an early page fault handler, allowing for on-demand building of the identity mapping. With that, !KASLR configurations do not use the EFI page table anymore but switch to a kernel-controlled one. The main part of this series adds the support for that new exchange mechanism. The goal has been to keep this as much as possibly separate from the core x86 code by concentrating the machinery in two SEV-ES-specific files: arch/x86/kernel/sev-es-shared.c arch/x86/kernel/sev-es.c Other interaction with core x86 code has been kept at minimum and behind static keys to minimize the performance impact on !SEV-ES setups. Work by Joerg Roedel and Thomas Lendacky and others" * tag 'x86_seves_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (73 commits) x86/sev-es: Use GHCB accessor for setting the MMIO scratch buffer x86/sev-es: Check required CPU features for SEV-ES x86/efi: Add GHCB mappings when SEV-ES is active x86/sev-es: Handle NMI State x86/sev-es: Support CPU offline/online x86/head/64: Don't call verify_cpu() on starting APs x86/smpboot: Load TSS and getcpu GDT entry before loading IDT x86/realmode: Setup AP jump table x86/realmode: Add SEV-ES specific trampoline entry point x86/vmware: Add VMware-specific handling for VMMCALL under SEV-ES x86/kvm: Add KVM-specific VMMCALL handling under SEV-ES x86/paravirt: Allow hypervisor-specific VMMCALL handling under SEV-ES x86/sev-es: Handle #DB Events x86/sev-es: Handle #AC Events x86/sev-es: Handle VMMCALL Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle INVD Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle RDTSC(P) Events ...
543 lines
15 KiB
C
543 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 1991, 1992 Linus Torvalds
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* Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
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* Copyright (C) 2011 Don Zickus Red Hat, Inc.
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*
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* Pentium III FXSR, SSE support
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* Gareth Hughes <gareth@valinux.com>, May 2000
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*/
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/*
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* Handle hardware traps and faults.
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*/
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#include <linux/spinlock.h>
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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#include <linux/sched/debug.h>
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#include <linux/nmi.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/hardirq.h>
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#include <linux/ratelimit.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/atomic.h>
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#include <linux/sched/clock.h>
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#include <asm/cpu_entry_area.h>
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#include <asm/traps.h>
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#include <asm/mach_traps.h>
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#include <asm/nmi.h>
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#include <asm/x86_init.h>
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#include <asm/reboot.h>
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#include <asm/cache.h>
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#include <asm/nospec-branch.h>
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#include <asm/sev-es.h>
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#define CREATE_TRACE_POINTS
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#include <trace/events/nmi.h>
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struct nmi_desc {
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raw_spinlock_t lock;
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struct list_head head;
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};
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static struct nmi_desc nmi_desc[NMI_MAX] =
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{
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{
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.lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock),
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.head = LIST_HEAD_INIT(nmi_desc[0].head),
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},
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{
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.lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
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.head = LIST_HEAD_INIT(nmi_desc[1].head),
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},
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{
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.lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock),
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.head = LIST_HEAD_INIT(nmi_desc[2].head),
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},
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{
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.lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock),
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.head = LIST_HEAD_INIT(nmi_desc[3].head),
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},
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};
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struct nmi_stats {
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unsigned int normal;
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unsigned int unknown;
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unsigned int external;
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unsigned int swallow;
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};
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static DEFINE_PER_CPU(struct nmi_stats, nmi_stats);
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static int ignore_nmis __read_mostly;
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int unknown_nmi_panic;
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/*
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* Prevent NMI reason port (0x61) being accessed simultaneously, can
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* only be used in NMI handler.
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*/
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static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
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static int __init setup_unknown_nmi_panic(char *str)
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{
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unknown_nmi_panic = 1;
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return 1;
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}
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__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
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#define nmi_to_desc(type) (&nmi_desc[type])
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static u64 nmi_longest_ns = 1 * NSEC_PER_MSEC;
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static int __init nmi_warning_debugfs(void)
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{
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debugfs_create_u64("nmi_longest_ns", 0644,
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arch_debugfs_dir, &nmi_longest_ns);
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return 0;
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}
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fs_initcall(nmi_warning_debugfs);
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static void nmi_check_duration(struct nmiaction *action, u64 duration)
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{
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int remainder_ns, decimal_msecs;
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if (duration < nmi_longest_ns || duration < action->max_duration)
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return;
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action->max_duration = duration;
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remainder_ns = do_div(duration, (1000 * 1000));
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decimal_msecs = remainder_ns / 1000;
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printk_ratelimited(KERN_INFO
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"INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n",
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action->handler, duration, decimal_msecs);
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}
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static int nmi_handle(unsigned int type, struct pt_regs *regs)
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{
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struct nmi_desc *desc = nmi_to_desc(type);
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struct nmiaction *a;
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int handled=0;
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rcu_read_lock();
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/*
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* NMIs are edge-triggered, which means if you have enough
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* of them concurrently, you can lose some because only one
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* can be latched at any given time. Walk the whole list
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* to handle those situations.
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*/
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list_for_each_entry_rcu(a, &desc->head, list) {
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int thishandled;
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u64 delta;
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delta = sched_clock();
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thishandled = a->handler(type, regs);
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handled += thishandled;
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delta = sched_clock() - delta;
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trace_nmi_handler(a->handler, (int)delta, thishandled);
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nmi_check_duration(a, delta);
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}
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rcu_read_unlock();
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/* return total number of NMI events handled */
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return handled;
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}
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NOKPROBE_SYMBOL(nmi_handle);
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int __register_nmi_handler(unsigned int type, struct nmiaction *action)
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{
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struct nmi_desc *desc = nmi_to_desc(type);
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unsigned long flags;
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if (!action->handler)
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return -EINVAL;
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raw_spin_lock_irqsave(&desc->lock, flags);
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/*
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* Indicate if there are multiple registrations on the
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* internal NMI handler call chains (SERR and IO_CHECK).
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*/
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WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head));
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WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head));
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/*
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* some handlers need to be executed first otherwise a fake
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* event confuses some handlers (kdump uses this flag)
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*/
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if (action->flags & NMI_FLAG_FIRST)
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list_add_rcu(&action->list, &desc->head);
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else
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list_add_tail_rcu(&action->list, &desc->head);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(__register_nmi_handler);
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void unregister_nmi_handler(unsigned int type, const char *name)
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{
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struct nmi_desc *desc = nmi_to_desc(type);
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struct nmiaction *n;
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unsigned long flags;
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raw_spin_lock_irqsave(&desc->lock, flags);
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list_for_each_entry_rcu(n, &desc->head, list) {
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/*
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* the name passed in to describe the nmi handler
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* is used as the lookup key
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*/
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if (!strcmp(n->name, name)) {
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WARN(in_nmi(),
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"Trying to free NMI (%s) from NMI context!\n", n->name);
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list_del_rcu(&n->list);
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break;
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}
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}
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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synchronize_rcu();
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}
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EXPORT_SYMBOL_GPL(unregister_nmi_handler);
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static void
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pci_serr_error(unsigned char reason, struct pt_regs *regs)
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{
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/* check to see if anyone registered against these types of errors */
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if (nmi_handle(NMI_SERR, regs))
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return;
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pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
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reason, smp_processor_id());
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if (panic_on_unrecovered_nmi)
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nmi_panic(regs, "NMI: Not continuing");
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pr_emerg("Dazed and confused, but trying to continue\n");
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/* Clear and disable the PCI SERR error line. */
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reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
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outb(reason, NMI_REASON_PORT);
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}
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NOKPROBE_SYMBOL(pci_serr_error);
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static void
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io_check_error(unsigned char reason, struct pt_regs *regs)
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{
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unsigned long i;
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/* check to see if anyone registered against these types of errors */
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if (nmi_handle(NMI_IO_CHECK, regs))
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return;
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pr_emerg(
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"NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
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reason, smp_processor_id());
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show_regs(regs);
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if (panic_on_io_nmi) {
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nmi_panic(regs, "NMI IOCK error: Not continuing");
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/*
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* If we end up here, it means we have received an NMI while
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* processing panic(). Simply return without delaying and
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* re-enabling NMIs.
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*/
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return;
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}
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/* Re-enable the IOCK line, wait for a few seconds */
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reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
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outb(reason, NMI_REASON_PORT);
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i = 20000;
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while (--i) {
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touch_nmi_watchdog();
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udelay(100);
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}
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reason &= ~NMI_REASON_CLEAR_IOCHK;
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outb(reason, NMI_REASON_PORT);
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}
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NOKPROBE_SYMBOL(io_check_error);
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static void
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unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
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{
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int handled;
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/*
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* Use 'false' as back-to-back NMIs are dealt with one level up.
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* Of course this makes having multiple 'unknown' handlers useless
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* as only the first one is ever run (unless it can actually determine
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* if it caused the NMI)
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*/
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handled = nmi_handle(NMI_UNKNOWN, regs);
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if (handled) {
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__this_cpu_add(nmi_stats.unknown, handled);
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return;
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}
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__this_cpu_add(nmi_stats.unknown, 1);
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pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
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reason, smp_processor_id());
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pr_emerg("Do you have a strange power saving mode enabled?\n");
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if (unknown_nmi_panic || panic_on_unrecovered_nmi)
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nmi_panic(regs, "NMI: Not continuing");
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pr_emerg("Dazed and confused, but trying to continue\n");
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}
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NOKPROBE_SYMBOL(unknown_nmi_error);
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static DEFINE_PER_CPU(bool, swallow_nmi);
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static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
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static noinstr void default_do_nmi(struct pt_regs *regs)
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{
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unsigned char reason = 0;
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int handled;
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bool b2b = false;
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/*
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* CPU-specific NMI must be processed before non-CPU-specific
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* NMI, otherwise we may lose it, because the CPU-specific
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* NMI can not be detected/processed on other CPUs.
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*/
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/*
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* Back-to-back NMIs are interesting because they can either
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* be two NMI or more than two NMIs (any thing over two is dropped
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* due to NMI being edge-triggered). If this is the second half
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* of the back-to-back NMI, assume we dropped things and process
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* more handlers. Otherwise reset the 'swallow' NMI behaviour
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*/
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if (regs->ip == __this_cpu_read(last_nmi_rip))
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b2b = true;
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else
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__this_cpu_write(swallow_nmi, false);
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__this_cpu_write(last_nmi_rip, regs->ip);
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instrumentation_begin();
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handled = nmi_handle(NMI_LOCAL, regs);
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__this_cpu_add(nmi_stats.normal, handled);
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if (handled) {
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/*
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* There are cases when a NMI handler handles multiple
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* events in the current NMI. One of these events may
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* be queued for in the next NMI. Because the event is
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* already handled, the next NMI will result in an unknown
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* NMI. Instead lets flag this for a potential NMI to
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* swallow.
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*/
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if (handled > 1)
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__this_cpu_write(swallow_nmi, true);
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goto out;
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}
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/*
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* Non-CPU-specific NMI: NMI sources can be processed on any CPU.
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*
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* Another CPU may be processing panic routines while holding
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* nmi_reason_lock. Check if the CPU issued the IPI for crash dumping,
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* and if so, call its callback directly. If there is no CPU preparing
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* crash dump, we simply loop here.
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*/
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while (!raw_spin_trylock(&nmi_reason_lock)) {
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run_crash_ipi_callback(regs);
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cpu_relax();
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}
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reason = x86_platform.get_nmi_reason();
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if (reason & NMI_REASON_MASK) {
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if (reason & NMI_REASON_SERR)
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pci_serr_error(reason, regs);
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else if (reason & NMI_REASON_IOCHK)
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io_check_error(reason, regs);
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#ifdef CONFIG_X86_32
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/*
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* Reassert NMI in case it became active
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* meanwhile as it's edge-triggered:
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*/
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reassert_nmi();
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#endif
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__this_cpu_add(nmi_stats.external, 1);
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raw_spin_unlock(&nmi_reason_lock);
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goto out;
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}
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raw_spin_unlock(&nmi_reason_lock);
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/*
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* Only one NMI can be latched at a time. To handle
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* this we may process multiple nmi handlers at once to
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* cover the case where an NMI is dropped. The downside
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* to this approach is we may process an NMI prematurely,
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* while its real NMI is sitting latched. This will cause
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* an unknown NMI on the next run of the NMI processing.
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*
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* We tried to flag that condition above, by setting the
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* swallow_nmi flag when we process more than one event.
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* This condition is also only present on the second half
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* of a back-to-back NMI, so we flag that condition too.
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*
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* If both are true, we assume we already processed this
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* NMI previously and we swallow it. Otherwise we reset
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* the logic.
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*
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* There are scenarios where we may accidentally swallow
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* a 'real' unknown NMI. For example, while processing
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* a perf NMI another perf NMI comes in along with a
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* 'real' unknown NMI. These two NMIs get combined into
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* one (as described above). When the next NMI gets
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* processed, it will be flagged by perf as handled, but
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* no one will know that there was a 'real' unknown NMI sent
|
|
* also. As a result it gets swallowed. Or if the first
|
|
* perf NMI returns two events handled then the second
|
|
* NMI will get eaten by the logic below, again losing a
|
|
* 'real' unknown NMI. But this is the best we can do
|
|
* for now.
|
|
*/
|
|
if (b2b && __this_cpu_read(swallow_nmi))
|
|
__this_cpu_add(nmi_stats.swallow, 1);
|
|
else
|
|
unknown_nmi_error(reason, regs);
|
|
|
|
out:
|
|
instrumentation_end();
|
|
}
|
|
|
|
/*
|
|
* NMIs can page fault or hit breakpoints which will cause it to lose
|
|
* its NMI context with the CPU when the breakpoint or page fault does an IRET.
|
|
*
|
|
* As a result, NMIs can nest if NMIs get unmasked due an IRET during
|
|
* NMI processing. On x86_64, the asm glue protects us from nested NMIs
|
|
* if the outer NMI came from kernel mode, but we can still nest if the
|
|
* outer NMI came from user mode.
|
|
*
|
|
* To handle these nested NMIs, we have three states:
|
|
*
|
|
* 1) not running
|
|
* 2) executing
|
|
* 3) latched
|
|
*
|
|
* When no NMI is in progress, it is in the "not running" state.
|
|
* When an NMI comes in, it goes into the "executing" state.
|
|
* Normally, if another NMI is triggered, it does not interrupt
|
|
* the running NMI and the HW will simply latch it so that when
|
|
* the first NMI finishes, it will restart the second NMI.
|
|
* (Note, the latch is binary, thus multiple NMIs triggering,
|
|
* when one is running, are ignored. Only one NMI is restarted.)
|
|
*
|
|
* If an NMI executes an iret, another NMI can preempt it. We do not
|
|
* want to allow this new NMI to run, but we want to execute it when the
|
|
* first one finishes. We set the state to "latched", and the exit of
|
|
* the first NMI will perform a dec_return, if the result is zero
|
|
* (NOT_RUNNING), then it will simply exit the NMI handler. If not, the
|
|
* dec_return would have set the state to NMI_EXECUTING (what we want it
|
|
* to be when we are running). In this case, we simply jump back to
|
|
* rerun the NMI handler again, and restart the 'latched' NMI.
|
|
*
|
|
* No trap (breakpoint or page fault) should be hit before nmi_restart,
|
|
* thus there is no race between the first check of state for NOT_RUNNING
|
|
* and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
|
|
* at this point.
|
|
*
|
|
* In case the NMI takes a page fault, we need to save off the CR2
|
|
* because the NMI could have preempted another page fault and corrupt
|
|
* the CR2 that is about to be read. As nested NMIs must be restarted
|
|
* and they can not take breakpoints or page faults, the update of the
|
|
* CR2 must be done before converting the nmi state back to NOT_RUNNING.
|
|
* Otherwise, there would be a race of another nested NMI coming in
|
|
* after setting state to NOT_RUNNING but before updating the nmi_cr2.
|
|
*/
|
|
enum nmi_states {
|
|
NMI_NOT_RUNNING = 0,
|
|
NMI_EXECUTING,
|
|
NMI_LATCHED,
|
|
};
|
|
static DEFINE_PER_CPU(enum nmi_states, nmi_state);
|
|
static DEFINE_PER_CPU(unsigned long, nmi_cr2);
|
|
static DEFINE_PER_CPU(unsigned long, nmi_dr7);
|
|
|
|
DEFINE_IDTENTRY_RAW(exc_nmi)
|
|
{
|
|
bool irq_state;
|
|
|
|
/*
|
|
* Re-enable NMIs right here when running as an SEV-ES guest. This might
|
|
* cause nested NMIs, but those can be handled safely.
|
|
*/
|
|
sev_es_nmi_complete();
|
|
|
|
if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id()))
|
|
return;
|
|
|
|
if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) {
|
|
this_cpu_write(nmi_state, NMI_LATCHED);
|
|
return;
|
|
}
|
|
this_cpu_write(nmi_state, NMI_EXECUTING);
|
|
this_cpu_write(nmi_cr2, read_cr2());
|
|
nmi_restart:
|
|
|
|
/*
|
|
* Needs to happen before DR7 is accessed, because the hypervisor can
|
|
* intercept DR7 reads/writes, turning those into #VC exceptions.
|
|
*/
|
|
sev_es_ist_enter(regs);
|
|
|
|
this_cpu_write(nmi_dr7, local_db_save());
|
|
|
|
irq_state = idtentry_enter_nmi(regs);
|
|
|
|
inc_irq_stat(__nmi_count);
|
|
|
|
if (!ignore_nmis)
|
|
default_do_nmi(regs);
|
|
|
|
idtentry_exit_nmi(regs, irq_state);
|
|
|
|
local_db_restore(this_cpu_read(nmi_dr7));
|
|
|
|
sev_es_ist_exit();
|
|
|
|
if (unlikely(this_cpu_read(nmi_cr2) != read_cr2()))
|
|
write_cr2(this_cpu_read(nmi_cr2));
|
|
if (this_cpu_dec_return(nmi_state))
|
|
goto nmi_restart;
|
|
|
|
if (user_mode(regs))
|
|
mds_user_clear_cpu_buffers();
|
|
}
|
|
|
|
void stop_nmi(void)
|
|
{
|
|
ignore_nmis++;
|
|
}
|
|
|
|
void restart_nmi(void)
|
|
{
|
|
ignore_nmis--;
|
|
}
|
|
|
|
/* reset the back-to-back NMI logic */
|
|
void local_touch_nmi(void)
|
|
{
|
|
__this_cpu_write(last_nmi_rip, 0);
|
|
}
|
|
EXPORT_SYMBOL_GPL(local_touch_nmi);
|