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36c4da4f55
linux/drivers/clk/renesas
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Niklas Söderlund 36c4da4f55 clk: renesas: rcar-gen3: Add HS400 quirk for SD clock 
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400
needs a quirk to function properly. The reason for the quirk is that
there are two settings which produces same divider value for the SDn
clock. On the effected boards the one currently selected results in
HS400 not working.

This change uses the same method as the Gen2 CPG driver and simply
ignores the first clock setting as this is the offending one when
selecting the settings. Which of the two possible settings is used have
no effect for SDR104.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-07 11:45:06 +01:00
..
clk-div6.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-div6.h We have two changes to the core framework this time around. The first being a 2017-11-17 20:04:24 -08:00
clk-emev2.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-mstp.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a73a4.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a7740.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a7778.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a7779.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-rcar-gen2.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-rz.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-sh73a0.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
Kconfig Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
Makefile clk: renesas: cpg-mssr: Add r8a774c0 support 2018-09-19 16:42:14 +02:00
r7s9210-cpg-mssr.c clk: renesas: r7s9210: Add USB clocks 2018-11-13 09:58:51 +01:00
r8a774a1-cpg-mssr.c clk: renesas: r8a774a1: Add CPEX clock 2018-12-04 10:29:37 +01:00
r8a774c0-cpg-mssr.c clk: renesas: cpg-mssr: Add r8a774c0 support 2018-09-19 16:42:14 +02:00
r8a7743-cpg-mssr.c Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
r8a7745-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7790-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7791-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7792-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7794-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7795-cpg-mssr.c clk: renesas: r8a7795: Add CPEX clock 2018-12-04 10:29:41 +01:00
r8a7796-cpg-mssr.c clk: renesas: r8a7796: Add CPEX clock 2018-12-04 10:29:43 +01:00
r8a77470-cpg-mssr.c clk: renesas: cpg-mssr: Add r8a77470 support 2018-04-16 13:39:40 +02:00
r8a77965-cpg-mssr.c clk: renesas: r8a77965: Add CPEX clock 2018-12-04 10:29:46 +01:00
r8a77970-cpg-mssr.c clk: renesas: r8a77970: Add CPEX clock 2018-12-04 10:29:48 +01:00
r8a77980-cpg-mssr.c clk: renesas: r8a77980: Add CMT clocks 2018-09-03 09:58:33 +02:00
r8a77990-cpg-mssr.c clk: renesas: r8a77990: Correct parent clock of DU 2018-12-04 10:29:51 +01:00
r8a77995-cpg-mssr.c clk: renesas: r8a77995: Simplify PLL3 multiplier/divider 2018-12-04 10:30:16 +01:00
r9a06g032-clocks.c clk: renesas: r9a06g032: Fix UART34567 clock rate 2018-09-11 11:57:25 +02:00
rcar-gen2-cpg.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
rcar-gen2-cpg.h clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
rcar-gen3-cpg.c clk: renesas: rcar-gen3: Add HS400 quirk for SD clock 2018-12-07 11:45:06 +01:00
rcar-gen3-cpg.h Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
rcar-usb2-clock-sel.c clk: renesas: use SPDX identifier for Renesas drivers 2018-08-30 18:18:44 -07:00
renesas-cpg-mssr.c Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
renesas-cpg-mssr.h Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00