7c6a6641c2
The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks.
Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after
disable as this clock signal is used by hardware to turn ON memories in
LPASS. Also add the external mclk to interface external MI2S.
Fixes: a9dd26639d ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-6-git-send-email-quic_c_skakit@quicinc.com
465 lines
13 KiB
C
465 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "gdsc.h"
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enum {
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P_BI_TCXO,
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P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN,
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P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC,
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P_LPASS_CORE_CC_DIG_PLL_OUT_ODD,
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};
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static const struct pll_vco lucid_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 614.4MHz configuration */
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static const struct alpha_pll_config lpass_core_cc_dig_pll_config = {
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.l = 0x20,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0xB2923BBC,
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.user_ctl_val = 0x00005100,
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.user_ctl_hi_val = 0x00050805,
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.user_ctl_hi1_val = 0x00000000,
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};
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static struct clk_alpha_pll lpass_core_cc_dig_pll = {
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.offset = 0x1000,
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.vco_table = lucid_vco,
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.num_vco = ARRAY_SIZE(lucid_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "lpass_core_cc_dig_pll",
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.parent_data = &(const struct clk_parent_data){
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.index = 0,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_ops,
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},
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},
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};
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static const struct clk_div_table post_div_table_lpass_core_cc_dig_pll_out_odd[] = {
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{ 0x5, 5 },
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{ }
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};
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static struct clk_alpha_pll_postdiv lpass_core_cc_dig_pll_out_odd = {
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.offset = 0x1000,
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.post_div_shift = 12,
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.post_div_table = post_div_table_lpass_core_cc_dig_pll_out_odd,
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.num_post_div = ARRAY_SIZE(post_div_table_lpass_core_cc_dig_pll_out_odd),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "lpass_core_cc_dig_pll_out_odd",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_dig_pll.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ops,
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},
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};
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static struct clk_regmap_div lpass_core_cc_dig_pll_out_main_div_clk_src = {
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.reg = 0x1054,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "lpass_core_cc_dig_pll_out_main_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_dig_pll.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static const struct parent_map lpass_core_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 5 },
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};
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static const struct clk_parent_data lpass_core_cc_parent_data_0[] = {
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{ .index = 0 },
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{ .hw = &lpass_core_cc_dig_pll_out_odd.clkr.hw },
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};
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static const struct parent_map lpass_core_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN, 1 },
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{ P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 2 },
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};
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static const struct clk_parent_data lpass_core_cc_parent_data_ao_2[] = {
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{ .index = 1 },
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{ .hw = &lpass_core_cc_dig_pll.clkr.hw },
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{ .hw = &lpass_core_cc_dig_pll_out_main_div_clk_src.clkr.hw },
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};
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static const struct freq_tbl ftbl_lpass_core_cc_core_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(51200000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 6, 0, 0),
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F(102400000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 3, 0, 0),
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F(204800000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN, 3, 0, 0),
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{ }
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};
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static struct clk_rcg2 lpass_core_cc_core_clk_src = {
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.cmd_rcgr = 0x1d000,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = lpass_core_cc_parent_map_2,
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.freq_tbl = ftbl_lpass_core_cc_core_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_core_clk_src",
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.parent_data = lpass_core_cc_parent_data_ao_2,
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.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_ao_2),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_lpass_core_cc_ext_if0_clk_src[] = {
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F(256000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 32),
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F(512000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 16),
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F(768000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 16),
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F(1024000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 8),
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F(1536000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 8),
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F(2048000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 4),
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F(3072000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 4),
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F(4096000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 2),
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F(6144000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 2),
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F(8192000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 0, 0),
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F(9600000, P_BI_TCXO, 2, 0, 0),
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F(12288000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 0, 0),
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(24576000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 5, 0, 0),
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{ }
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};
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static struct clk_rcg2 lpass_core_cc_ext_if0_clk_src = {
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.cmd_rcgr = 0x10000,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = lpass_core_cc_parent_map_0,
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.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_ext_if0_clk_src",
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.parent_data = lpass_core_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = {
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.cmd_rcgr = 0x11000,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = lpass_core_cc_parent_map_0,
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.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_ext_if1_clk_src",
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.parent_data = lpass_core_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src = {
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.cmd_rcgr = 0x20000,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = lpass_core_cc_parent_map_0,
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.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_ext_mclk0_clk_src",
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.parent_data = lpass_core_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch lpass_core_cc_core_clk = {
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.halt_reg = 0x1f000,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x1f000,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x1f000,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_core_clk",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_core_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_aon_ops,
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},
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},
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};
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static struct clk_branch lpass_core_cc_ext_if0_ibit_clk = {
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.halt_reg = 0x10018,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x10018,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_ext_if0_ibit_clk",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_ext_if0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_core_cc_ext_if1_ibit_clk = {
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.halt_reg = 0x11018,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x11018,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_ext_if1_ibit_clk",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_ext_if1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_core_cc_lpm_core_clk = {
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.halt_reg = 0x1e000,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1e000,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_lpm_core_clk",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_core_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_core_cc_lpm_mem0_core_clk = {
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.halt_reg = 0x1e004,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1e004,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_lpm_mem0_core_clk",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_core_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_core_cc_ext_mclk0_clk = {
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.halt_reg = 0x20014,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x20014,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_ext_mclk0_clk",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_ext_mclk0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = {
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.halt_reg = 0x23000,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x23000,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x23000,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "lpass_core_cc_sysnoc_mport_core_clk",
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.parent_hws = (const struct clk_hw*[]){
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&lpass_core_cc_core_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc lpass_core_cc_lpass_core_hm_gdsc = {
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.gdscr = 0x0,
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.pd = {
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.name = "lpass_core_cc_lpass_core_hm_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = RETAIN_FF_ENABLE,
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};
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static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
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[LPASS_CORE_CC_CORE_CLK] = &lpass_core_cc_core_clk.clkr,
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[LPASS_CORE_CC_CORE_CLK_SRC] = &lpass_core_cc_core_clk_src.clkr,
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[LPASS_CORE_CC_DIG_PLL] = &lpass_core_cc_dig_pll.clkr,
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[LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC] =
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&lpass_core_cc_dig_pll_out_main_div_clk_src.clkr,
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[LPASS_CORE_CC_DIG_PLL_OUT_ODD] = &lpass_core_cc_dig_pll_out_odd.clkr,
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[LPASS_CORE_CC_EXT_IF0_CLK_SRC] = &lpass_core_cc_ext_if0_clk_src.clkr,
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[LPASS_CORE_CC_EXT_IF0_IBIT_CLK] = &lpass_core_cc_ext_if0_ibit_clk.clkr,
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[LPASS_CORE_CC_EXT_IF1_CLK_SRC] = &lpass_core_cc_ext_if1_clk_src.clkr,
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[LPASS_CORE_CC_EXT_IF1_IBIT_CLK] = &lpass_core_cc_ext_if1_ibit_clk.clkr,
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[LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
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[LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
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[LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
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[LPASS_CORE_CC_EXT_MCLK0_CLK] = &lpass_core_cc_ext_mclk0_clk.clkr,
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[LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] = &lpass_core_cc_ext_mclk0_clk_src.clkr,
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};
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static struct regmap_config lpass_core_cc_sc7280_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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};
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static const struct qcom_cc_desc lpass_core_cc_sc7280_desc = {
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.config = &lpass_core_cc_sc7280_regmap_config,
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.clks = lpass_core_cc_sc7280_clocks,
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.num_clks = ARRAY_SIZE(lpass_core_cc_sc7280_clocks),
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};
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static const struct of_device_id lpass_core_cc_sc7280_match_table[] = {
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{ .compatible = "qcom,sc7280-lpasscorecc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7280_match_table);
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static struct gdsc *lpass_core_hm_sc7280_gdscs[] = {
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[LPASS_CORE_CC_LPASS_CORE_HM_GDSC] = &lpass_core_cc_lpass_core_hm_gdsc,
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};
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static const struct qcom_cc_desc lpass_core_hm_sc7280_desc = {
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.config = &lpass_core_cc_sc7280_regmap_config,
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.gdscs = lpass_core_hm_sc7280_gdscs,
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.num_gdscs = ARRAY_SIZE(lpass_core_hm_sc7280_gdscs),
|
|
};
|
|
|
|
static int lpass_core_cc_sc7280_probe(struct platform_device *pdev)
|
|
{
|
|
const struct qcom_cc_desc *desc;
|
|
struct regmap *regmap;
|
|
|
|
lpass_core_cc_sc7280_regmap_config.name = "lpass_core_cc";
|
|
lpass_core_cc_sc7280_regmap_config.max_register = 0x4f004;
|
|
desc = &lpass_core_cc_sc7280_desc;
|
|
|
|
regmap = qcom_cc_map(pdev, desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
clk_lucid_pll_configure(&lpass_core_cc_dig_pll, regmap, &lpass_core_cc_dig_pll_config);
|
|
|
|
return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7280_desc, regmap);
|
|
}
|
|
|
|
static struct platform_driver lpass_core_cc_sc7280_driver = {
|
|
.probe = lpass_core_cc_sc7280_probe,
|
|
.driver = {
|
|
.name = "lpass_core_cc-sc7280",
|
|
.of_match_table = lpass_core_cc_sc7280_match_table,
|
|
},
|
|
};
|
|
|
|
static int lpass_hm_core_probe(struct platform_device *pdev)
|
|
{
|
|
const struct qcom_cc_desc *desc;
|
|
|
|
lpass_core_cc_sc7280_regmap_config.name = "lpass_hm_core";
|
|
lpass_core_cc_sc7280_regmap_config.max_register = 0x24;
|
|
desc = &lpass_core_hm_sc7280_desc;
|
|
|
|
return qcom_cc_probe_by_index(pdev, 0, desc);
|
|
}
|
|
|
|
static const struct of_device_id lpass_hm_sc7280_match_table[] = {
|
|
{ .compatible = "qcom,sc7280-lpasshm" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, lpass_hm_sc7280_match_table);
|
|
|
|
static struct platform_driver lpass_hm_sc7280_driver = {
|
|
.probe = lpass_hm_core_probe,
|
|
.driver = {
|
|
.name = "lpass_hm-sc7280",
|
|
.of_match_table = lpass_hm_sc7280_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init lpass_core_cc_sc7280_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&lpass_hm_sc7280_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return platform_driver_register(&lpass_core_cc_sc7280_driver);
|
|
}
|
|
subsys_initcall(lpass_core_cc_sc7280_init);
|
|
|
|
static void __exit lpass_core_cc_sc7280_exit(void)
|
|
{
|
|
platform_driver_unregister(&lpass_core_cc_sc7280_driver);
|
|
platform_driver_unregister(&lpass_hm_sc7280_driver);
|
|
}
|
|
module_exit(lpass_core_cc_sc7280_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI LPASS_CORE_CC SC7280 Driver");
|
|
MODULE_LICENSE("GPL v2");
|