31c6ed4e89
When (ARCH_STARFIVE [=n] && COMPILE_TEST [=y] && RESET_CONTROLLER [=n]), RESET_STARFIVE_JH7110 can't be selected by CLK_STARFIVE_JH7110_SYS and CLK_STARFIVE_JH7110_AON. Add a condition `if RESET_CONTROLLER` to fix it. Also, delete redundant selected options of CLK_STARFIVE_JH7110_AON because these options are already selected by the dependency. Fixes:edab7204af
("clk: starfive: Add StarFive JH7110 system clock driver") Fixes:b2ab3c94f4
("clk: starfive: Add StarFive JH7110 always-on clock driver") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230418123756.62495-2-hal.feng@starfivetech.com Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
42 lines
1.1 KiB
Plaintext
42 lines
1.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
|
|
|
|
config CLK_STARFIVE_JH71X0
|
|
bool
|
|
|
|
config CLK_STARFIVE_JH7100
|
|
bool "StarFive JH7100 clock support"
|
|
depends on ARCH_STARFIVE || COMPILE_TEST
|
|
select CLK_STARFIVE_JH71X0
|
|
default ARCH_STARFIVE
|
|
help
|
|
Say yes here to support the clock controller on the StarFive JH7100
|
|
SoC.
|
|
|
|
config CLK_STARFIVE_JH7100_AUDIO
|
|
tristate "StarFive JH7100 audio clock support"
|
|
depends on CLK_STARFIVE_JH7100
|
|
select CLK_STARFIVE_JH71X0
|
|
default m if ARCH_STARFIVE
|
|
help
|
|
Say Y or M here to support the audio clocks on the StarFive JH7100
|
|
SoC.
|
|
|
|
config CLK_STARFIVE_JH7110_SYS
|
|
bool "StarFive JH7110 system clock support"
|
|
depends on ARCH_STARFIVE || COMPILE_TEST
|
|
select AUXILIARY_BUS
|
|
select CLK_STARFIVE_JH71X0
|
|
select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
|
|
default ARCH_STARFIVE
|
|
help
|
|
Say yes here to support the system clock controller on the
|
|
StarFive JH7110 SoC.
|
|
|
|
config CLK_STARFIVE_JH7110_AON
|
|
tristate "StarFive JH7110 always-on clock support"
|
|
depends on CLK_STARFIVE_JH7110_SYS
|
|
default m if ARCH_STARFIVE
|
|
help
|
|
Say yes here to support the always-on clock controller on the
|
|
StarFive JH7110 SoC.
|