ac4eead379
The current dsb API is not really prepared to handle multithread access.
I was debugging an issue that ended up fixed by commit a096883dda2c
("drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA") and was
puzzled how these atomic operations were guaranteeing atomicity.
if (atomic_add_return(1, &dsb->refcount) != 1)
return dsb;
Thread A could still be initializing dsb struct (and even fail in the
middle) while thread B would take a reference and use it (even
derefencing a NULL cmd_buf).
I don't think the atomic operations here will help much if this were
to support multithreaded scenario in future, so just remove them to
avoid confusion.
v2: Use refcount++ != 0 instead of ++refcount != 1 (from Ville)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191111205024.22853-2-lucas.demarchi@intel.com
Link: https://patchwork.freedesktop.org/patch/msgid/20191116011539.18230-1-lucas.demarchi@intel.com
53 lines
1005 B
C
53 lines
1005 B
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef _INTEL_DSB_H
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#define _INTEL_DSB_H
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#include <linux/types.h>
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#include "i915_reg.h"
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struct intel_crtc;
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struct i915_vma;
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enum dsb_id {
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INVALID_DSB = -1,
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DSB1,
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DSB2,
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DSB3,
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MAX_DSB_PER_PIPE
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};
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struct intel_dsb {
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long refcount;
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enum dsb_id id;
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u32 *cmd_buf;
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struct i915_vma *vma;
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/*
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* free_pos will point the first free entry position
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* and help in calculating tail of command buffer.
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*/
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int free_pos;
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/*
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* ins_start_offset will help to store start address of the dsb
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* instuction and help in identifying the batch of auto-increment
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* register.
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*/
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u32 ins_start_offset;
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};
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struct intel_dsb *
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intel_dsb_get(struct intel_crtc *crtc);
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void intel_dsb_put(struct intel_dsb *dsb);
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void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
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void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
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u32 val);
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void intel_dsb_commit(struct intel_dsb *dsb);
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#endif
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