37276e00da
The max larb number that a iommu HW support is 8(larb0~larb7 in the below
diagram).
If the larb's number is over 8, we use a sub_common for merging
several larbs into one larb. At this case, we will extend larb_id:
bit[11:9] means common-id;
bit[8:7] means subcommon-id;
>From these two variables, we could get the real larb number when
translation fault happen.
The diagram is as below:
EMI
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IOMMU
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-----------------
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common1 common0
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-----------------
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smi common
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------------------------------------
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3'd0 3'd1 3'd2 3'd3 ... 3'd7 <-common_id(max is 8)
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Larb0 Larb1 | Larb3 ... Larb7
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smi sub common
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--------------------------
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2'd0 2'd1 2'd2 2'd3 <-sub_common_id(max is 4)
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Larb8 Larb9 Larb10 Larb11
In this patch we extend larb_remap[] to larb_remap[8][4] for this.
larb_remap[x][y]: x means common-id above, y means subcommon_id above.
We can also distinguish if the M4U HW has sub_common by HAS_SUB_COMM
macro.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20200703044127.27438-7-chao.hao@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
96 lines
2.0 KiB
C
96 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Honghui Zhang <honghui.zhang@mediatek.com>
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*/
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#ifndef _MTK_IOMMU_H_
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#define _MTK_IOMMU_H_
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/io-pgtable.h>
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#include <linux/iommu.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <soc/mediatek/smi.h>
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#define MTK_LARB_COM_MAX 8
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#define MTK_LARB_SUBCOM_MAX 4
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struct mtk_iommu_suspend_reg {
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union {
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u32 standard_axi_mode;/* v1 */
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u32 misc_ctrl;/* v2 */
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};
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u32 dcm_dis;
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u32 ctrl_reg;
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u32 int_control0;
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u32 int_main_control;
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u32 ivrp_paddr;
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u32 vld_pa_rng;
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};
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enum mtk_iommu_plat {
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M4U_MT2701,
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M4U_MT2712,
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M4U_MT8173,
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M4U_MT8183,
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};
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struct mtk_iommu_plat_data {
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enum mtk_iommu_plat m4u_plat;
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u32 flags;
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u32 inv_sel_reg;
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unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
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};
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struct mtk_iommu_domain;
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struct mtk_iommu_data {
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void __iomem *base;
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int irq;
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struct device *dev;
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struct clk *bclk;
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phys_addr_t protect_base; /* protect memory base */
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struct mtk_iommu_suspend_reg reg;
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struct mtk_iommu_domain *m4u_dom;
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struct iommu_group *m4u_group;
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bool enable_4GB;
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spinlock_t tlb_lock; /* lock for tlb range flush */
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struct iommu_device iommu;
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const struct mtk_iommu_plat_data *plat_data;
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struct list_head list;
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struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
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};
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static inline int compare_of(struct device *dev, void *data)
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{
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return dev->of_node == data;
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}
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static inline void release_of(struct device *dev, void *data)
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{
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of_node_put(data);
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}
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static inline int mtk_iommu_bind(struct device *dev)
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{
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struct mtk_iommu_data *data = dev_get_drvdata(dev);
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return component_bind_all(dev, &data->larb_imu);
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}
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static inline void mtk_iommu_unbind(struct device *dev)
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{
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struct mtk_iommu_data *data = dev_get_drvdata(dev);
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component_unbind_all(dev, &data->larb_imu);
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}
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#endif
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