Tushar Behera 37746c9a2d clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3} ... commit 688f7d8c9f ("clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3} to fix the wrong clock value. Though this fixed issue with Arndale, it created regressions for other boards like Snow. On Exynos5250, sclk_mmc<n> is generated like below (as per the clock names in drivers/clk/samsung/clk-exynos5250.c) mout_group1_p ==> mout_mmc<n> ==> div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n> Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence div_mmc_pre<n> was not getting referred in kernel code and depending on its value set during preboot, sclk_mmc<n> value was different for various boards. Setting the correct clock generation path should fix the issues reported in above referenced commit. The changes committed during the earlier patch has also been reverted here. Reported-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Olof Johansson <olof@lixom.net>		2013-04-23 19:51:30 -07:00
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clk-exynos4.c	clk: exynos4: export clocks required for fimc-is	2013-04-08 23:43:54 +09:00
clk-exynos5250.c	clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}	2013-04-23 19:51:30 -07:00
clk-exynos5440.c	clk: exynos4: Add support for SoC-specific register save list	2013-04-04 15:51:22 +09:00
clk-pll.c	clk: samsung: Remove unimplemented ops for pll	2013-04-04 15:51:09 +09:00
clk-pll.h	clk: samsung: add pll clock registration helper functions	2013-03-25 18:16:37 +09:00
clk.c	clk: samsung: Fix compilation error	2013-04-08 23:43:12 +09:00
clk.h	clk: exynos4: Add support for SoC-specific register save list	2013-04-04 15:51:22 +09:00
Makefile	clk: exynos5440: register clocks using common clock framework	2013-03-25 18:17:05 +09:00