4828556dca
In cases where we don't reference another schema, 'additionalProperties' can be used instead. This is preferred for now as 'unevaluatedProperties' support isn't implemented yet. In a few cases, this means adding some missing property definitions of which most are for SPI bus properties. 'unevaluatedProperties' is not going to work for the SPI bus properties anyways as they are evaluated from the parent node, not the SPI child node. Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20201005183830.486085-3-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
132 lines
3.6 KiB
YAML
132 lines
3.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner H6 CPU OPP Device Tree Bindings
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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description: |
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For some SoCs, the CPU frequency subset and voltage value of each
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OPP varies based on the silicon variant in use. Allwinner Process
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Voltage Scaling Tables defines the voltage and frequency value based
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on the speedbin blown in the efuse combination. The
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sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
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provide the OPP framework with required information.
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properties:
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compatible:
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const: allwinner,sun50i-h6-operating-points
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nvmem-cells:
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description: |
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A phandle pointing to a nvmem-cells node representing the efuse
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registers that has information about the speedbin that is used
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to select the right frequency/voltage value pair. Please refer
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the for nvmem-cells bindings
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Documentation/devicetree/bindings/nvmem/nvmem.txt and also
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examples below.
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opp-shared: true
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required:
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- compatible
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- nvmem-cells
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patternProperties:
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"opp-[0-9]+":
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type: object
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properties:
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opp-hz: true
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patternProperties:
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"opp-microvolt-.*": true
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required:
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- opp-hz
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- opp-microvolt-speed0
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- opp-microvolt-speed1
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- opp-microvolt-speed2
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unevaluatedProperties: false
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additionalProperties: false
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examples:
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- |
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cpu_opp_table: opp-table {
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compatible = "allwinner,sun50i-h6-operating-points";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-480000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt-speed0 = <880000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp-720000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt-speed0 = <880000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp-816000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt-speed0 = <880000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp-888000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <888000000>;
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opp-microvolt-speed0 = <940000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp-1080000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1080000000>;
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opp-microvolt-speed0 = <1060000>;
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opp-microvolt-speed1 = <880000>;
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opp-microvolt-speed2 = <840000>;
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};
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opp-1320000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1320000000>;
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opp-microvolt-speed0 = <1160000>;
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opp-microvolt-speed1 = <940000>;
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opp-microvolt-speed2 = <900000>;
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};
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opp-1488000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1488000000>;
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opp-microvolt-speed0 = <1160000>;
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opp-microvolt-speed1 = <1000000>;
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opp-microvolt-speed2 = <960000>;
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};
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};
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...
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