176ada03e3
Turing introduced a new simplified page kind scheme, reducing the number of possible page kinds from 256 to 16. It also is the first NVIDIA GPU in which the highest possible page kind value is not reserved as an "invalid" page kind. To address this, the invalid page kind is made an explicit property of the MMU HAL, and a new table of page kinds is added to the tu102 MMU HAL. One hardware change not addressed here is that 0x00 is technically no longer a supported page kind, and pitch surfaces are instead intended to share the block-linear generic page kind 0x06. However, because that will be a rather invasive change to nouveau and 0x00 still works fine in practice on Turing hardware, addressing this new behavior is deferred. Signed-off-by: James Jones <jajones@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
43 lines
775 B
C
43 lines
775 B
C
#ifndef __NVIF_IF0008_H__
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#define __NVIF_IF0008_H__
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struct nvif_mmu_v0 {
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__u8 version;
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__u8 dmabits;
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__u8 heap_nr;
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__u8 type_nr;
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__u16 kind_nr;
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};
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#define NVIF_MMU_V0_HEAP 0x00
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#define NVIF_MMU_V0_TYPE 0x01
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#define NVIF_MMU_V0_KIND 0x02
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struct nvif_mmu_heap_v0 {
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__u8 version;
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__u8 index;
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__u8 pad02[6];
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__u64 size;
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};
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struct nvif_mmu_type_v0 {
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__u8 version;
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__u8 index;
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__u8 heap;
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__u8 vram;
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__u8 host;
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__u8 comp;
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__u8 disp;
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__u8 kind;
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__u8 mappable;
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__u8 coherent;
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__u8 uncached;
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};
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struct nvif_mmu_kind_v0 {
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__u8 version;
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__u8 kind_inv;
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__u16 count;
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__u8 data[];
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};
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#endif
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