f10b83de1f
If the BAR is zero size, it indicates it was never successfully mapped. Ensure that the BAR is valid during initialization before attempting to use it. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
255 lines
6.6 KiB
C
255 lines
6.6 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv50.h"
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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static void
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nv50_bar_flush(struct nvkm_bar *base)
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{
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struct nv50_bar *bar = nv50_bar(base);
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struct nvkm_device *device = bar->base.subdev.device;
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unsigned long flags;
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spin_lock_irqsave(&bar->base.lock, flags);
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nvkm_wr32(device, 0x00330c, 0x00000001);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x00330c) & 0x00000002))
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break;
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);
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spin_unlock_irqrestore(&bar->base.lock, flags);
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}
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struct nvkm_vmm *
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nv50_bar_bar1_vmm(struct nvkm_bar *base)
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{
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return nv50_bar(base)->bar1_vmm;
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}
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void
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nv50_bar_bar1_wait(struct nvkm_bar *base)
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{
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nvkm_bar_flush(base);
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}
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void
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nv50_bar_bar1_fini(struct nvkm_bar *bar)
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{
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nvkm_wr32(bar->subdev.device, 0x001708, 0x00000000);
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}
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void
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nv50_bar_bar1_init(struct nvkm_bar *base)
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{
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struct nvkm_device *device = base->subdev.device;
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struct nv50_bar *bar = nv50_bar(base);
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nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
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}
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struct nvkm_vmm *
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nv50_bar_bar2_vmm(struct nvkm_bar *base)
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{
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return nv50_bar(base)->bar2_vmm;
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}
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void
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nv50_bar_bar2_fini(struct nvkm_bar *bar)
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{
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nvkm_wr32(bar->subdev.device, 0x00170c, 0x00000000);
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}
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void
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nv50_bar_bar2_init(struct nvkm_bar *base)
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{
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struct nvkm_device *device = base->subdev.device;
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struct nv50_bar *bar = nv50_bar(base);
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nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);
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nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);
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nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4);
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}
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void
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nv50_bar_init(struct nvkm_bar *base)
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{
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struct nv50_bar *bar = nv50_bar(base);
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struct nvkm_device *device = bar->base.subdev.device;
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int i;
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for (i = 0; i < 8; i++)
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nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000);
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}
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int
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nv50_bar_oneinit(struct nvkm_bar *base)
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{
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struct nv50_bar *bar = nv50_bar(base);
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struct nvkm_device *device = bar->base.subdev.device;
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static struct lock_class_key bar1_lock;
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static struct lock_class_key bar2_lock;
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u64 start, limit, size;
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int ret;
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ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem,
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&bar->pad);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd);
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if (ret)
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return ret;
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/* BAR2 */
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start = 0x0100000000ULL;
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size = device->func->resource_size(device, 3);
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if (!size)
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return -ENOMEM;
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limit = start + size;
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ret = nvkm_vmm_new(device, start, limit-- - start, NULL, 0,
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&bar2_lock, "bar2", &bar->bar2_vmm);
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if (ret)
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return ret;
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atomic_inc(&bar->bar2_vmm->engref[NVKM_SUBDEV_BAR]);
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bar->bar2_vmm->debug = bar->base.subdev.debug;
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ret = nvkm_vmm_boot(bar->bar2_vmm);
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if (ret)
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return ret;
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ret = nvkm_vmm_join(bar->bar2_vmm, bar->mem->memory);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2);
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if (ret)
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return ret;
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nvkm_kmap(bar->bar2);
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nvkm_wo32(bar->bar2, 0x00, 0x7fc00000);
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nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit));
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nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start));
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nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 |
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upper_32_bits(start));
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nvkm_wo32(bar->bar2, 0x10, 0x00000000);
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nvkm_wo32(bar->bar2, 0x14, 0x00000000);
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nvkm_done(bar->bar2);
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bar->base.subdev.oneinit = true;
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nvkm_bar_bar2_init(device);
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/* BAR1 */
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start = 0x0000000000ULL;
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size = device->func->resource_size(device, 1);
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if (!size)
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return -ENOMEM;
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limit = start + size;
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ret = nvkm_vmm_new(device, start, limit-- - start, NULL, 0,
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&bar1_lock, "bar1", &bar->bar1_vmm);
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if (ret)
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return ret;
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atomic_inc(&bar->bar1_vmm->engref[NVKM_SUBDEV_BAR]);
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bar->bar1_vmm->debug = bar->base.subdev.debug;
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ret = nvkm_vmm_join(bar->bar1_vmm, bar->mem->memory);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1);
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if (ret)
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return ret;
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nvkm_kmap(bar->bar1);
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nvkm_wo32(bar->bar1, 0x00, 0x7fc00000);
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nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit));
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nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start));
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nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 |
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upper_32_bits(start));
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nvkm_wo32(bar->bar1, 0x10, 0x00000000);
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nvkm_wo32(bar->bar1, 0x14, 0x00000000);
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nvkm_done(bar->bar1);
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return 0;
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}
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void *
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nv50_bar_dtor(struct nvkm_bar *base)
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{
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struct nv50_bar *bar = nv50_bar(base);
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if (bar->mem) {
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nvkm_gpuobj_del(&bar->bar1);
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nvkm_vmm_part(bar->bar1_vmm, bar->mem->memory);
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nvkm_vmm_unref(&bar->bar1_vmm);
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nvkm_gpuobj_del(&bar->bar2);
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nvkm_vmm_part(bar->bar2_vmm, bar->mem->memory);
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nvkm_vmm_unref(&bar->bar2_vmm);
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nvkm_gpuobj_del(&bar->pgd);
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nvkm_gpuobj_del(&bar->pad);
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nvkm_gpuobj_del(&bar->mem);
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}
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return bar;
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}
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int
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nv50_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device,
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int index, u32 pgd_addr, struct nvkm_bar **pbar)
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{
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struct nv50_bar *bar;
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if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL)))
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return -ENOMEM;
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nvkm_bar_ctor(func, device, index, &bar->base);
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bar->pgd_addr = pgd_addr;
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*pbar = &bar->base;
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return 0;
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}
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static const struct nvkm_bar_func
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nv50_bar_func = {
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.dtor = nv50_bar_dtor,
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.oneinit = nv50_bar_oneinit,
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.init = nv50_bar_init,
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.bar1.init = nv50_bar_bar1_init,
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.bar1.fini = nv50_bar_bar1_fini,
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.bar1.wait = nv50_bar_bar1_wait,
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.bar1.vmm = nv50_bar_bar1_vmm,
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.bar2.init = nv50_bar_bar2_init,
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.bar2.fini = nv50_bar_bar2_fini,
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.bar2.wait = nv50_bar_bar1_wait,
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.bar2.vmm = nv50_bar_bar2_vmm,
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.flush = nv50_bar_flush,
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};
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int
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nv50_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
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{
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return nv50_bar_new_(&nv50_bar_func, device, index, 0x1400, pbar);
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}
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