382ad0d957
As opposed to Spectrum-1, in which time stamps arrive through a pair of
dedicated events into a queue and later are being matched to the
corresponding packets, in Spectrum-2 we are reading the time stamps
directly from the CQE. Software can get the time stamp in UTC format
using CQEv2.
Add a time stamp field to 'struct mlxsw_skb_cb'. In
mlxsw_pci_cqe_{rdq,sdq}_handle() extract the time stamp from the CQE into
the new time stamp field. Note that the time stamp in the CQE is
represented by 38 bits, which is a short representation of UTC time.
Software should create the full time stamp using the global UTC clock.
Read UTC clock from hardware only for PTP packets which were trapped to CPU
with PTP0 trap ID (event packets).
Use the time stamp from the SKB when packet is received or transmitted.
Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
669 lines
21 KiB
C
669 lines
21 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
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/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
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#ifndef _MLXSW_CORE_H
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#define _MLXSW_CORE_H
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/gfp.h>
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#include <linux/types.h>
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#include <linux/skbuff.h>
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#include <linux/workqueue.h>
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#include <linux/net_namespace.h>
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#include <linux/auxiliary_bus.h>
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#include <net/devlink.h>
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#include "trap.h"
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#include "reg.h"
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#include "cmd.h"
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#include "resources.h"
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#include "../mlxfw/mlxfw.h"
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enum mlxsw_core_resource_id {
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MLXSW_CORE_RESOURCE_PORTS = 1,
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MLXSW_CORE_RESOURCE_MAX,
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};
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struct mlxsw_core;
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struct mlxsw_core_port;
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struct mlxsw_driver;
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struct mlxsw_bus;
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struct mlxsw_bus_info;
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struct mlxsw_fw_rev;
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unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core);
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void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core);
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struct mlxsw_linecards *mlxsw_core_linecards(struct mlxsw_core *mlxsw_core);
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void mlxsw_core_linecards_set(struct mlxsw_core *mlxsw_core,
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struct mlxsw_linecards *linecard);
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bool
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mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev,
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const struct mlxsw_fw_rev *req_rev);
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int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver);
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void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver);
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int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core,
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struct mlxfw_dev *mlxfw_dev,
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const struct firmware *firmware,
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struct netlink_ext_ack *extack);
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int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info,
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const struct mlxsw_bus *mlxsw_bus,
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void *bus_priv, bool reload,
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struct devlink *devlink,
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struct netlink_ext_ack *extack);
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void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, bool reload);
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struct mlxsw_tx_info {
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u16 local_port;
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bool is_emad;
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};
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struct mlxsw_rx_md_info {
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u32 cookie_index;
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u32 latency;
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u32 tx_congestion;
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union {
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/* Valid when 'tx_port_valid' is set. */
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u16 tx_sys_port;
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u16 tx_lag_id;
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};
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u16 tx_lag_port_index; /* Valid when 'tx_port_is_lag' is set. */
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u8 tx_tc;
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u8 latency_valid:1,
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tx_congestion_valid:1,
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tx_tc_valid:1,
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tx_port_valid:1,
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tx_port_is_lag:1,
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unused:3;
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};
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bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_tx_info *tx_info);
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int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
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const struct mlxsw_tx_info *tx_info);
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void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core,
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struct sk_buff *skb, u16 local_port);
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struct mlxsw_rx_listener {
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void (*func)(struct sk_buff *skb, u16 local_port, void *priv);
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u16 local_port;
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u8 mirror_reason;
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u16 trap_id;
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};
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struct mlxsw_event_listener {
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void (*func)(const struct mlxsw_reg_info *reg,
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char *payload, void *priv);
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enum mlxsw_event_trap_id trap_id;
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};
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struct mlxsw_listener {
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u16 trap_id;
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union {
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struct mlxsw_rx_listener rx_listener;
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struct mlxsw_event_listener event_listener;
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};
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enum mlxsw_reg_hpkt_action en_action; /* Action when enabled */
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enum mlxsw_reg_hpkt_action dis_action; /* Action when disabled */
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u8 en_trap_group; /* Trap group when enabled */
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u8 dis_trap_group; /* Trap group when disabled */
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u8 is_ctrl:1, /* should go via control buffer or not */
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is_event:1,
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enabled_on_register:1; /* Trap should be enabled when listener
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* is registered.
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*/
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};
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#define __MLXSW_RXL(_func, _trap_id, _en_action, _is_ctrl, _en_trap_group, \
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_dis_action, _enabled_on_register, _dis_trap_group, \
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_mirror_reason) \
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{ \
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.trap_id = MLXSW_TRAP_ID_##_trap_id, \
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.rx_listener = \
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{ \
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.func = _func, \
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.local_port = MLXSW_PORT_DONT_CARE, \
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.mirror_reason = _mirror_reason, \
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.trap_id = MLXSW_TRAP_ID_##_trap_id, \
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}, \
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.en_action = MLXSW_REG_HPKT_ACTION_##_en_action, \
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.dis_action = MLXSW_REG_HPKT_ACTION_##_dis_action, \
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.en_trap_group = MLXSW_REG_HTGT_TRAP_GROUP_##_en_trap_group, \
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.dis_trap_group = MLXSW_REG_HTGT_TRAP_GROUP_##_dis_trap_group, \
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.is_ctrl = _is_ctrl, \
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.enabled_on_register = _enabled_on_register, \
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}
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#define MLXSW_RXL(_func, _trap_id, _en_action, _is_ctrl, _trap_group, \
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_dis_action) \
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__MLXSW_RXL(_func, _trap_id, _en_action, _is_ctrl, _trap_group, \
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_dis_action, true, _trap_group, 0)
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#define MLXSW_RXL_DIS(_func, _trap_id, _en_action, _is_ctrl, _en_trap_group, \
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_dis_action, _dis_trap_group) \
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__MLXSW_RXL(_func, _trap_id, _en_action, _is_ctrl, _en_trap_group, \
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_dis_action, false, _dis_trap_group, 0)
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#define MLXSW_RXL_MIRROR(_func, _session_id, _trap_group, _mirror_reason) \
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__MLXSW_RXL(_func, MIRROR_SESSION##_session_id, TRAP_TO_CPU, false, \
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_trap_group, TRAP_TO_CPU, true, _trap_group, \
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_mirror_reason)
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#define MLXSW_EVENTL(_func, _trap_id, _trap_group) \
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{ \
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.trap_id = MLXSW_TRAP_ID_##_trap_id, \
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.event_listener = \
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{ \
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.func = _func, \
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.trap_id = MLXSW_TRAP_ID_##_trap_id, \
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}, \
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.en_action = MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, \
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.en_trap_group = MLXSW_REG_HTGT_TRAP_GROUP_##_trap_group, \
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.is_event = true, \
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.enabled_on_register = true, \
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}
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#define MLXSW_CORE_EVENTL(_func, _trap_id) \
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MLXSW_EVENTL(_func, _trap_id, CORE_EVENT)
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int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_rx_listener *rxl,
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void *priv, bool enabled);
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void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_rx_listener *rxl);
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int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_event_listener *el,
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void *priv);
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void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_event_listener *el);
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int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_listener *listener,
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void *priv);
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void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_listener *listener,
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void *priv);
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int mlxsw_core_traps_register(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_listener *listeners,
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size_t listeners_count, void *priv);
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void mlxsw_core_traps_unregister(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_listener *listeners,
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size_t listeners_count, void *priv);
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int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_listener *listener,
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bool enabled);
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typedef void mlxsw_reg_trans_cb_t(struct mlxsw_core *mlxsw_core, char *payload,
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size_t payload_len, unsigned long cb_priv);
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int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_reg_info *reg, char *payload,
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struct list_head *bulk_list,
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mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv);
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int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_reg_info *reg, char *payload,
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struct list_head *bulk_list,
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mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv);
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int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list);
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int mlxsw_reg_query(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_reg_info *reg, char *payload);
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int mlxsw_reg_write(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_reg_info *reg, char *payload);
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struct mlxsw_rx_info {
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bool is_lag;
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union {
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u16 sys_port;
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u16 lag_id;
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} u;
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u16 lag_port_index;
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u8 mirror_reason;
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int trap_id;
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};
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void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
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struct mlxsw_rx_info *rx_info);
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void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core,
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u16 lag_id, u8 port_index, u16 local_port);
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u16 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core,
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u16 lag_id, u8 port_index);
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void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core,
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u16 lag_id, u16 local_port);
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void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port);
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int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port,
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u8 slot_index, u32 port_number, bool split,
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u32 split_port_subnumber,
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bool splittable, u32 lanes,
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const unsigned char *switch_id,
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unsigned char switch_id_len);
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void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port);
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int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core,
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void *port_driver_priv,
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const unsigned char *switch_id,
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unsigned char switch_id_len);
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void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core);
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void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u16 local_port,
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void *port_driver_priv, struct net_device *dev);
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void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u16 local_port,
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void *port_driver_priv);
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void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u16 local_port,
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void *port_driver_priv);
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enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core,
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u16 local_port);
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struct devlink_port *
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mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core,
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u16 local_port);
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struct mlxsw_linecard *
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mlxsw_core_port_linecard_get(struct mlxsw_core *mlxsw_core,
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u16 local_port);
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void mlxsw_core_ports_remove_selected(struct mlxsw_core *mlxsw_core,
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bool (*selector)(void *priv,
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u16 local_port),
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void *priv);
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struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core);
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int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay);
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bool mlxsw_core_schedule_work(struct work_struct *work);
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void mlxsw_core_flush_owq(void);
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int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox,
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struct mlxsw_res *res);
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#define MLXSW_CONFIG_PROFILE_SWID_COUNT 8
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struct mlxsw_swid_config {
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u8 used_type:1,
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used_properties:1;
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u8 type;
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u8 properties;
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};
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struct mlxsw_config_profile {
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u16 used_max_vepa_channels:1,
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used_max_mid:1,
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used_max_pgt:1,
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used_max_system_port:1,
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used_max_vlan_groups:1,
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used_max_regions:1,
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used_flood_tables:1,
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used_flood_mode:1,
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used_max_ib_mc:1,
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used_max_pkey:1,
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used_ar_sec:1,
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used_adaptive_routing_group_cap:1,
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used_ubridge:1,
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used_kvd_sizes:1,
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used_cqe_time_stamp_type:1;
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u8 max_vepa_channels;
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u16 max_mid;
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u16 max_pgt;
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u16 max_system_port;
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u16 max_vlan_groups;
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u16 max_regions;
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u8 max_flood_tables;
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u8 max_vid_flood_tables;
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u8 flood_mode;
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u8 max_fid_offset_flood_tables;
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u16 fid_offset_flood_table_size;
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u8 max_fid_flood_tables;
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u16 fid_flood_table_size;
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u16 max_ib_mc;
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u16 max_pkey;
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u8 ar_sec;
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u16 adaptive_routing_group_cap;
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u8 arn;
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u8 ubridge;
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u32 kvd_linear_size;
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u8 kvd_hash_single_parts;
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u8 kvd_hash_double_parts;
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u8 cqe_time_stamp_type;
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struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT];
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};
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struct mlxsw_driver {
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struct list_head list;
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const char *kind;
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size_t priv_size;
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const struct mlxsw_fw_rev *fw_req_rev;
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const char *fw_filename;
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int (*init)(struct mlxsw_core *mlxsw_core,
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const struct mlxsw_bus_info *mlxsw_bus_info,
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struct netlink_ext_ack *extack);
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void (*fini)(struct mlxsw_core *mlxsw_core);
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int (*port_type_set)(struct mlxsw_core *mlxsw_core, u16 local_port,
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enum devlink_port_type new_type);
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int (*port_split)(struct mlxsw_core *mlxsw_core, u16 local_port,
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unsigned int count, struct netlink_ext_ack *extack);
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int (*port_unsplit)(struct mlxsw_core *mlxsw_core, u16 local_port,
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struct netlink_ext_ack *extack);
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void (*ports_remove_selected)(struct mlxsw_core *mlxsw_core,
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bool (*selector)(void *priv,
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u16 local_port),
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void *priv);
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int (*sb_pool_get)(struct mlxsw_core *mlxsw_core,
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unsigned int sb_index, u16 pool_index,
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struct devlink_sb_pool_info *pool_info);
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int (*sb_pool_set)(struct mlxsw_core *mlxsw_core,
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unsigned int sb_index, u16 pool_index, u32 size,
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enum devlink_sb_threshold_type threshold_type,
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struct netlink_ext_ack *extack);
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int (*sb_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port,
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unsigned int sb_index, u16 pool_index,
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u32 *p_threshold);
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int (*sb_port_pool_set)(struct mlxsw_core_port *mlxsw_core_port,
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unsigned int sb_index, u16 pool_index,
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u32 threshold, struct netlink_ext_ack *extack);
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int (*sb_tc_pool_bind_get)(struct mlxsw_core_port *mlxsw_core_port,
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unsigned int sb_index, u16 tc_index,
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enum devlink_sb_pool_type pool_type,
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u16 *p_pool_index, u32 *p_threshold);
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int (*sb_tc_pool_bind_set)(struct mlxsw_core_port *mlxsw_core_port,
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unsigned int sb_index, u16 tc_index,
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enum devlink_sb_pool_type pool_type,
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u16 pool_index, u32 threshold,
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struct netlink_ext_ack *extack);
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int (*sb_occ_snapshot)(struct mlxsw_core *mlxsw_core,
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unsigned int sb_index);
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int (*sb_occ_max_clear)(struct mlxsw_core *mlxsw_core,
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unsigned int sb_index);
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int (*sb_occ_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port,
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unsigned int sb_index, u16 pool_index,
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u32 *p_cur, u32 *p_max);
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int (*sb_occ_tc_port_bind_get)(struct mlxsw_core_port *mlxsw_core_port,
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unsigned int sb_index, u16 tc_index,
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enum devlink_sb_pool_type pool_type,
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u32 *p_cur, u32 *p_max);
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int (*trap_init)(struct mlxsw_core *mlxsw_core,
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const struct devlink_trap *trap, void *trap_ctx);
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void (*trap_fini)(struct mlxsw_core *mlxsw_core,
|
|
const struct devlink_trap *trap, void *trap_ctx);
|
|
int (*trap_action_set)(struct mlxsw_core *mlxsw_core,
|
|
const struct devlink_trap *trap,
|
|
enum devlink_trap_action action,
|
|
struct netlink_ext_ack *extack);
|
|
int (*trap_group_init)(struct mlxsw_core *mlxsw_core,
|
|
const struct devlink_trap_group *group);
|
|
int (*trap_group_set)(struct mlxsw_core *mlxsw_core,
|
|
const struct devlink_trap_group *group,
|
|
const struct devlink_trap_policer *policer,
|
|
struct netlink_ext_ack *extack);
|
|
int (*trap_policer_init)(struct mlxsw_core *mlxsw_core,
|
|
const struct devlink_trap_policer *policer);
|
|
void (*trap_policer_fini)(struct mlxsw_core *mlxsw_core,
|
|
const struct devlink_trap_policer *policer);
|
|
int (*trap_policer_set)(struct mlxsw_core *mlxsw_core,
|
|
const struct devlink_trap_policer *policer,
|
|
u64 rate, u64 burst,
|
|
struct netlink_ext_ack *extack);
|
|
int (*trap_policer_counter_get)(struct mlxsw_core *mlxsw_core,
|
|
const struct devlink_trap_policer *policer,
|
|
u64 *p_drops);
|
|
void (*txhdr_construct)(struct sk_buff *skb,
|
|
const struct mlxsw_tx_info *tx_info);
|
|
int (*resources_register)(struct mlxsw_core *mlxsw_core);
|
|
int (*kvd_sizes_get)(struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_config_profile *profile,
|
|
u64 *p_single_size, u64 *p_double_size,
|
|
u64 *p_linear_size);
|
|
int (*params_register)(struct mlxsw_core *mlxsw_core);
|
|
void (*params_unregister)(struct mlxsw_core *mlxsw_core);
|
|
|
|
/* Notify a driver that a timestamped packet was transmitted. Driver
|
|
* is responsible for freeing the passed-in SKB.
|
|
*/
|
|
void (*ptp_transmitted)(struct mlxsw_core *mlxsw_core,
|
|
struct sk_buff *skb, u16 local_port);
|
|
|
|
u8 txhdr_len;
|
|
const struct mlxsw_config_profile *profile;
|
|
bool sdq_supports_cqe_v2;
|
|
};
|
|
|
|
int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_config_profile *profile,
|
|
u64 *p_single_size, u64 *p_double_size,
|
|
u64 *p_linear_size);
|
|
|
|
u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core);
|
|
u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core);
|
|
|
|
u32 mlxsw_core_read_utc_sec(struct mlxsw_core *mlxsw_core);
|
|
u32 mlxsw_core_read_utc_nsec(struct mlxsw_core *mlxsw_core);
|
|
|
|
bool mlxsw_core_sdq_supports_cqe_v2(struct mlxsw_core *mlxsw_core);
|
|
|
|
void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core);
|
|
|
|
bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core,
|
|
enum mlxsw_res_id res_id);
|
|
|
|
#define MLXSW_CORE_RES_VALID(mlxsw_core, short_res_id) \
|
|
mlxsw_core_res_valid(mlxsw_core, MLXSW_RES_ID_##short_res_id)
|
|
|
|
u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core,
|
|
enum mlxsw_res_id res_id);
|
|
|
|
#define MLXSW_CORE_RES_GET(mlxsw_core, short_res_id) \
|
|
mlxsw_core_res_get(mlxsw_core, MLXSW_RES_ID_##short_res_id)
|
|
|
|
static inline struct net *mlxsw_core_net(struct mlxsw_core *mlxsw_core)
|
|
{
|
|
return devlink_net(priv_to_devlink(mlxsw_core));
|
|
}
|
|
|
|
#define MLXSW_BUS_F_TXRX BIT(0)
|
|
#define MLXSW_BUS_F_RESET BIT(1)
|
|
|
|
struct mlxsw_bus {
|
|
const char *kind;
|
|
int (*init)(void *bus_priv, struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_config_profile *profile,
|
|
struct mlxsw_res *res);
|
|
void (*fini)(void *bus_priv);
|
|
bool (*skb_transmit_busy)(void *bus_priv,
|
|
const struct mlxsw_tx_info *tx_info);
|
|
int (*skb_transmit)(void *bus_priv, struct sk_buff *skb,
|
|
const struct mlxsw_tx_info *tx_info);
|
|
int (*cmd_exec)(void *bus_priv, u16 opcode, u8 opcode_mod,
|
|
u32 in_mod, bool out_mbox_direct,
|
|
char *in_mbox, size_t in_mbox_size,
|
|
char *out_mbox, size_t out_mbox_size,
|
|
u8 *p_status);
|
|
u32 (*read_frc_h)(void *bus_priv);
|
|
u32 (*read_frc_l)(void *bus_priv);
|
|
u32 (*read_utc_sec)(void *bus_priv);
|
|
u32 (*read_utc_nsec)(void *bus_priv);
|
|
u8 features;
|
|
};
|
|
|
|
struct mlxsw_fw_rev {
|
|
u16 major;
|
|
u16 minor;
|
|
u16 subminor;
|
|
u16 can_reset_minor;
|
|
};
|
|
|
|
struct mlxsw_bus_info {
|
|
const char *device_kind;
|
|
const char *device_name;
|
|
struct device *dev;
|
|
struct mlxsw_fw_rev fw_rev;
|
|
u8 vsd[MLXSW_CMD_BOARDINFO_VSD_LEN];
|
|
u8 psid[MLXSW_CMD_BOARDINFO_PSID_LEN];
|
|
u8 low_frequency:1,
|
|
read_clock_capable:1;
|
|
};
|
|
|
|
struct mlxsw_hwmon;
|
|
|
|
#ifdef CONFIG_MLXSW_CORE_HWMON
|
|
|
|
int mlxsw_hwmon_init(struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_bus_info *mlxsw_bus_info,
|
|
struct mlxsw_hwmon **p_hwmon);
|
|
void mlxsw_hwmon_fini(struct mlxsw_hwmon *mlxsw_hwmon);
|
|
|
|
#else
|
|
|
|
static inline int mlxsw_hwmon_init(struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_bus_info *mlxsw_bus_info,
|
|
struct mlxsw_hwmon **p_hwmon)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void mlxsw_hwmon_fini(struct mlxsw_hwmon *mlxsw_hwmon)
|
|
{
|
|
}
|
|
|
|
#endif
|
|
|
|
struct mlxsw_thermal;
|
|
|
|
#ifdef CONFIG_MLXSW_CORE_THERMAL
|
|
|
|
int mlxsw_thermal_init(struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_bus_info *mlxsw_bus_info,
|
|
struct mlxsw_thermal **p_thermal);
|
|
void mlxsw_thermal_fini(struct mlxsw_thermal *thermal);
|
|
|
|
#else
|
|
|
|
static inline int mlxsw_thermal_init(struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_bus_info *mlxsw_bus_info,
|
|
struct mlxsw_thermal **p_thermal)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void mlxsw_thermal_fini(struct mlxsw_thermal *thermal)
|
|
{
|
|
}
|
|
|
|
#endif
|
|
|
|
enum mlxsw_devlink_param_id {
|
|
MLXSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
|
|
MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
|
|
};
|
|
|
|
struct mlxsw_cqe_ts {
|
|
u8 sec;
|
|
u32 nsec;
|
|
};
|
|
|
|
struct mlxsw_skb_cb {
|
|
union {
|
|
struct mlxsw_tx_info tx_info;
|
|
struct mlxsw_rx_md_info rx_md_info;
|
|
};
|
|
struct mlxsw_cqe_ts cqe_ts;
|
|
};
|
|
|
|
static inline struct mlxsw_skb_cb *mlxsw_skb_cb(struct sk_buff *skb)
|
|
{
|
|
BUILD_BUG_ON(sizeof(mlxsw_skb_cb) > sizeof(skb->cb));
|
|
return (struct mlxsw_skb_cb *) skb->cb;
|
|
}
|
|
|
|
struct mlxsw_linecards;
|
|
|
|
enum mlxsw_linecard_status_event_type {
|
|
MLXSW_LINECARD_STATUS_EVENT_TYPE_PROVISION,
|
|
MLXSW_LINECARD_STATUS_EVENT_TYPE_UNPROVISION,
|
|
};
|
|
|
|
struct mlxsw_linecard_bdev;
|
|
|
|
struct mlxsw_linecard_device_info {
|
|
u16 fw_major;
|
|
u16 fw_minor;
|
|
u16 fw_sub_minor;
|
|
char psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE];
|
|
};
|
|
|
|
struct mlxsw_linecard {
|
|
u8 slot_index;
|
|
struct mlxsw_linecards *linecards;
|
|
struct devlink_linecard *devlink_linecard;
|
|
struct mutex lock; /* Locks accesses to the linecard structure */
|
|
char name[MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN];
|
|
char mbct_pl[MLXSW_REG_MBCT_LEN]; /* Too big for stack */
|
|
enum mlxsw_linecard_status_event_type status_event_type_to;
|
|
struct delayed_work status_event_to_dw;
|
|
u8 provisioned:1,
|
|
ready:1,
|
|
active:1;
|
|
u16 hw_revision;
|
|
u16 ini_version;
|
|
struct mlxsw_linecard_bdev *bdev;
|
|
struct {
|
|
struct mlxsw_linecard_device_info info;
|
|
u8 index;
|
|
} device;
|
|
};
|
|
|
|
struct mlxsw_linecard_types_info;
|
|
|
|
struct mlxsw_linecards {
|
|
struct mlxsw_core *mlxsw_core;
|
|
const struct mlxsw_bus_info *bus_info;
|
|
u8 count;
|
|
struct mlxsw_linecard_types_info *types_info;
|
|
struct list_head event_ops_list;
|
|
struct mutex event_ops_list_lock; /* Locks accesses to event ops list */
|
|
struct mlxsw_linecard linecards[];
|
|
};
|
|
|
|
static inline struct mlxsw_linecard *
|
|
mlxsw_linecard_get(struct mlxsw_linecards *linecards, u8 slot_index)
|
|
{
|
|
return &linecards->linecards[slot_index - 1];
|
|
}
|
|
|
|
int mlxsw_linecard_devlink_info_get(struct mlxsw_linecard *linecard,
|
|
struct devlink_info_req *req,
|
|
struct netlink_ext_ack *extack);
|
|
int mlxsw_linecard_flash_update(struct devlink *linecard_devlink,
|
|
struct mlxsw_linecard *linecard,
|
|
const struct firmware *firmware,
|
|
struct netlink_ext_ack *extack);
|
|
|
|
int mlxsw_linecards_init(struct mlxsw_core *mlxsw_core,
|
|
const struct mlxsw_bus_info *bus_info);
|
|
void mlxsw_linecards_fini(struct mlxsw_core *mlxsw_core);
|
|
|
|
typedef void mlxsw_linecards_event_op_t(struct mlxsw_core *mlxsw_core,
|
|
u8 slot_index, void *priv);
|
|
|
|
struct mlxsw_linecards_event_ops {
|
|
mlxsw_linecards_event_op_t *got_active;
|
|
mlxsw_linecards_event_op_t *got_inactive;
|
|
};
|
|
|
|
int mlxsw_linecards_event_ops_register(struct mlxsw_core *mlxsw_core,
|
|
struct mlxsw_linecards_event_ops *ops,
|
|
void *priv);
|
|
void mlxsw_linecards_event_ops_unregister(struct mlxsw_core *mlxsw_core,
|
|
struct mlxsw_linecards_event_ops *ops,
|
|
void *priv);
|
|
|
|
int mlxsw_linecard_bdev_add(struct mlxsw_linecard *linecard);
|
|
void mlxsw_linecard_bdev_del(struct mlxsw_linecard *linecard);
|
|
|
|
int mlxsw_linecard_driver_register(void);
|
|
void mlxsw_linecard_driver_unregister(void);
|
|
|
|
#endif
|