Conor Dooley 38a71fc048 riscv: dts: microchip: add mpfs's CAN controllers ...

PolarFire SoC has a pair of CAN controllers, but as they were
undocumented there were omitted from the device tree. Add them.

Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@microchip.com
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

2022-06-13 15:54:10 +02:00

..

boot

riscv: dts: microchip: add mpfs's CAN controllers

2022-06-13 15:54:10 +02:00

configs

RISC-V: configs: Configs that had RPMSG_CHAR now get RPMSG_CTRL

2022-04-26 08:19:53 -07:00

errata

riscv: add memory-type errata for T-Head

2022-05-11 21:36:33 -07:00

include

riscv: Move alternative length validation into subsection

2022-06-02 15:55:22 -07:00

kernel

Bitmap patches for 5.19-rc1

2022-06-04 14:04:27 -07:00

kvm

RISC-V: KVM: Introduce ISA extension register

2022-05-20 09:09:20 +05:30

lib

riscv: Fixed misaligned memory access. Fixed pointer comparison.

2022-03-10 10:24:04 -08:00

mm

riscv: mm: init: make pt_ops_set_[early|late|fixmap] static

2022-06-02 14:50:41 -07:00

net

riscv, bpf: Implement more atomic operations for RV64

2022-04-11 16:54:54 +02:00

purgatory

RISC-V: Add purgatory

2022-05-19 12:18:59 -07:00

Kbuild

riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild

2022-06-01 22:26:32 -07:00

Kconfig

RISC-V: Only default to spinwait on SBI-0.1 and M-mode

2022-06-01 18:59:26 -07:00

Kconfig.debug

RISC-V: Remove EARLY_PRINTK support

2018-12-17 10:23:46 -08:00

Kconfig.erratas

riscv: add memory-type errata for T-Head

2022-05-11 21:36:33 -07:00

Kconfig.socs

RISC-V Patches for the 5.19 Merge Window, Part 1

2022-05-31 14:10:54 -07:00

Makefile

riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild

2022-06-01 22:26:32 -07:00