57e7235aa1
Read the DSB element size from the device tree. Set the register bit that controls the DSB element size of the corresponding port. Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1695882586-10306-5-git-send-email-quic_taozha@quicinc.com
38 lines
1.0 KiB
C
38 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _CORESIGHT_CORESIGHT_TPDA_H
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#define _CORESIGHT_CORESIGHT_TPDA_H
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#define TPDA_CR (0x000)
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#define TPDA_Pn_CR(n) (0x004 + (n * 4))
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/* Aggregator port enable bit */
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#define TPDA_Pn_CR_ENA BIT(0)
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/* Aggregator port DSB data set element size bit */
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#define TPDA_Pn_CR_DSBSIZE BIT(8)
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#define TPDA_MAX_INPORTS 32
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/* Bits 6 ~ 12 is for atid value */
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#define TPDA_CR_ATID GENMASK(12, 6)
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/**
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* struct tpda_drvdata - specifics associated to an TPDA component
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* @base: memory mapped base address for this component.
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* @dev: The device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @spinlock: lock for the drvdata value.
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* @enable: enable status of the component.
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*/
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struct tpda_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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spinlock_t spinlock;
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u8 atid;
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};
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#endif /* _CORESIGHT_CORESIGHT_TPDA_H */
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