Nicolas Pitre 3902a15e78 [ARM] xsc3: add highmem support to L2 cache handling code
On xsc3, L2 cache ops are possible only on virtual addresses.  The code
is rearranged so to have a linear progression requiring the least amount
of pte setups in the highmem case.  To protect the virtual mapping so
created, interrupts must be disabled currently up to a page worth of
address range.

The interrupt disabling is done in a way to minimize the overhead within
the inner loop.  The alternative would consist in separate code for
the highmem and non highmem compilation which is less preferable.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15 21:01:21 -04:00
..
2005-04-16 15:20:36 -07:00
2005-04-16 15:20:36 -07:00
2005-04-16 15:20:36 -07:00
2005-04-16 15:20:36 -07:00
2005-04-16 15:20:36 -07:00
2009-03-15 21:01:20 -04:00
2009-03-15 21:01:20 -04:00
2008-09-06 12:10:45 +01:00
2009-01-25 17:36:34 +00:00
2009-03-15 21:01:20 -04:00
2009-03-15 21:01:20 -04:00
2009-03-15 21:01:20 -04:00
2008-12-01 11:53:07 +00:00
2008-11-27 12:37:59 +00:00