Dan Williams 391785859e cxl/port: Move dport tracking to an xarray ... Reduce the complexity and the overhead of walking the topology to determine endpoint connectivity to root decoder interleave configurations. Note that cxl_detach_ep(), after it determines that the last @ep has departed and decides to delete the port, now needs to walk the dport array with the device_lock() held to remove entries. Previously list_splice_init() could be used atomically delete all dport entries at once and then perform entry tear down outside the lock. There is no list_splice_init() equivalent for the xarray. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/165784331647.1758207.6345820282285119339.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2022-07-21 17:19:24 -07:00
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core	cxl/port: Move dport tracking to an xarray	2022-07-21 17:19:24 -07:00
acpi.c	cxl/port: Record parent dport when adding ports	2022-07-21 17:19:24 -07:00
cxl.h	cxl/port: Move dport tracking to an xarray	2022-07-21 17:19:24 -07:00
cxlmem.h	cxl/hdm: Enumerate allocated DPA	2022-07-21 17:19:12 -07:00
cxlpci.h	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00
Kconfig	cxl/pci: Create PCI DOE mailbox's for memory devices	2022-07-19 15:38:04 -07:00
Makefile	PM: CXL: Disable suspend	2022-04-22 16:09:42 -07:00
mem.c	cxl/port: Record parent dport when adding ports	2022-07-21 17:19:24 -07:00
pci.c	cxl/pci: Create PCI DOE mailbox's for memory devices	2022-07-19 15:38:04 -07:00
pmem.c	cxl/mbox: Use __le32 in get,set_lsa mailbox structures	2022-06-21 14:09:00 -07:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00