linux/Documentation
Jakub Kicinski f84ad5cffd mlx5-updates-2023-06-06
1) Support 4 ports VF LAG, part 2/2
 2) Few extra trivial cleanup patches
 
 Shay Drory Says:
 ================
 
 Support 4 ports VF LAG, part 2/2
 
 This series continues the series[1] "Support 4 ports VF LAG, part1/2".
 This series adds support for 4 ports VF LAG (single FDB E-Switch).
 
 This series of patches refactoring LAG code that make assumptions
 about VF LAG supporting only two ports and then enable 4 ports VF LAG.
 
 Patch 1:
 - Fix for ib rep code
 Patches 2-5:
 - Refactors LAG layer.
 Patches 6-7:
 - Block LAG types which doesn't support 4 ports.
 Patch 8:
 - Enable 4 ports VF LAG.
 
 This series specifically allows HCAs with 4 ports to create a VF LAG
 with only 4 ports. It is not possible to create a VF LAG with 2 or 3
 ports using HCAs that have 4 ports.
 
 Currently, the Merged E-Switch feature only supports HCAs with 2 ports.
 However, upcoming patches will introduce support for HCAs with 4 ports.
 
 In order to activate VF LAG a user can execute:
 
 devlink dev eswitch set pci/0000:08:00.0 mode switchdev
 devlink dev eswitch set pci/0000:08:00.1 mode switchdev
 devlink dev eswitch set pci/0000:08:00.2 mode switchdev
 devlink dev eswitch set pci/0000:08:00.3 mode switchdev
 ip link add name bond0 type bond
 ip link set dev bond0 type bond mode 802.3ad
 ip link set dev eth2 master bond0
 ip link set dev eth3 master bond0
 ip link set dev eth4 master bond0
 ip link set dev eth5 master bond0
 
 Where eth2, eth3, eth4 and eth5 are net-interfaces of pci/0000:08:00.0
 pci/0000:08:00.1 pci/0000:08:00.2 pci/0000:08:00.3 respectively.
 
 User can verify LAG state and type via debugfs:
 /sys/kernel/debug/mlx5/0000\:08\:00.0/lag/state
 /sys/kernel/debug/mlx5/0000\:08\:00.0/lag/type
 
 [1]
 https://lore.kernel.org/netdev/20230601060118.154015-1-saeed@kernel.org/T/#mf1d2083780970ba277bfe721554d4925f03f36d1
 
 ================
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAmSA7/0ACgkQSD+KveBX
 +j4faQgApm14Id8QTB0rSj9tO1tJFtSgCcpDN9DtyYWuq3B0rGW9CPC1rPdaFOlt
 xst7PtEaCiJu7a7dwlH/kFLSAlXpZHdUZA+VG8JF0aYV8qOV/0R0xQKZgP68kwkn
 vFZqZCzA1vR6egK3AweAjKAVaqDKSSKVlFGXJGzyNpGMWpGEEKodlZKCH7Jd580F
 UFhCqbyY8vccMUa3cvrLVjePUjdM1xxsLKHWmYXTaN2NkoLvOYXnXThElu7skm96
 Uqv8B9t2FoojZPBxgiJtoGKZ516+1dozORq7ioQug3oG9P/vpTY5QnTMKSZpJUTH
 5cdSCdqii4UDPqfe0PtdEdE1O2aWig==
 =A44p
 -----END PGP SIGNATURE-----

Merge tag 'mlx5-updates-2023-06-06' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says:

====================
mlx5-updates-2023-06-06

1) Support 4 ports VF LAG, part 2/2
2) Few extra trivial cleanup patches

Shay Drory Says:
================

Support 4 ports VF LAG, part 2/2

This series continues the series[1] "Support 4 ports VF LAG, part1/2".
This series adds support for 4 ports VF LAG (single FDB E-Switch).

This series of patches refactoring LAG code that make assumptions
about VF LAG supporting only two ports and then enable 4 ports VF LAG.

Patch 1:
- Fix for ib rep code
Patches 2-5:
- Refactors LAG layer.
Patches 6-7:
- Block LAG types which doesn't support 4 ports.
Patch 8:
- Enable 4 ports VF LAG.

This series specifically allows HCAs with 4 ports to create a VF LAG
with only 4 ports. It is not possible to create a VF LAG with 2 or 3
ports using HCAs that have 4 ports.

Currently, the Merged E-Switch feature only supports HCAs with 2 ports.
However, upcoming patches will introduce support for HCAs with 4 ports.

In order to activate VF LAG a user can execute:

devlink dev eswitch set pci/0000:08:00.0 mode switchdev
devlink dev eswitch set pci/0000:08:00.1 mode switchdev
devlink dev eswitch set pci/0000:08:00.2 mode switchdev
devlink dev eswitch set pci/0000:08:00.3 mode switchdev
ip link add name bond0 type bond
ip link set dev bond0 type bond mode 802.3ad
ip link set dev eth2 master bond0
ip link set dev eth3 master bond0
ip link set dev eth4 master bond0
ip link set dev eth5 master bond0

Where eth2, eth3, eth4 and eth5 are net-interfaces of pci/0000:08:00.0
pci/0000:08:00.1 pci/0000:08:00.2 pci/0000:08:00.3 respectively.

User can verify LAG state and type via debugfs:
/sys/kernel/debug/mlx5/0000\:08\:00.0/lag/state
/sys/kernel/debug/mlx5/0000\:08\:00.0/lag/type

[1]
https://lore.kernel.org/netdev/20230601060118.154015-1-saeed@kernel.org/T/#mf1d2083780970ba277bfe721554d4925f03f36d1

================

* tag 'mlx5-updates-2023-06-06' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux:
  net/mlx5e: simplify condition after napi budget handling change
  mlx5/core: E-Switch, Allocate ECPF vport if it's an eswitch manager
  net/mlx5: Skip inline mode check after mlx5_eswitch_enable_locked() failure
  net/mlx5e: TC, refactor access to hash key
  net/mlx5e: Remove RX page cache leftovers
  net/mlx5e: Expose catastrophic steering error counters
  net/mlx5: Enable 4 ports VF LAG
  net/mlx5: LAG, block multiport eswitch LAG in case ldev have more than 2 ports
  net/mlx5: LAG, block multipath LAG in case ldev have more than 2 ports
  net/mlx5: LAG, change mlx5_shared_fdb_supported() to static
  net/mlx5: LAG, generalize handling of shared FDB
  net/mlx5: LAG, check if all eswitches are paired for shared FDB
  {net/RDMA}/mlx5: introduce lag_for_each_peer
  RDMA/mlx5: Free second uplink ib port
====================

Link: https://lore.kernel.org/r/20230607210410.88209-1-saeed@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2023-06-08 19:28:21 -07:00
..
2023-05-03 11:11:56 -07:00
2023-04-28 14:53:30 -07:00
2023-04-25 12:11:54 -07:00
2023-05-03 11:25:01 -07:00
2023-02-15 20:59:44 +01:00
2023-04-28 14:02:54 -07:00
2023-06-08 19:28:21 -07:00
2023-03-19 10:51:07 +00:00
2023-04-05 13:47:18 +00:00
2023-04-27 17:41:23 -07:00
2023-05-02 11:56:43 -07:00