396c56a9c6
The host controllers only support type 1, so there's not much else to test for. Some of the older controllers also supported type 2 accesses, but we've never supported those, and likely never will. Beyond that, the P1SEG test is meaningless for 32-bit mode, so rather than refactoring it, just kill the type 1 test off completely. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
160 lines
4.7 KiB
C
160 lines
4.7 KiB
C
/*
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* Low-Level PCI Support for the SH7780
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*
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* Copyright (C) 2005 - 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include "pci-sh4.h"
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#include <asm/mmu.h>
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#include <asm/sizes.h>
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static struct resource sh7785_io_resource = {
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.name = "SH7785_IO",
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.start = 0x1000,
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.end = SH7780_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource sh7785_mem_resource = {
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.name = "SH7785_mem",
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.start = SH7780_PCI_MEMORY_BASE,
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.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_channel sh7780_pci_controller = {
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.pci_ops = &sh4_pci_ops,
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.mem_resource = &sh7785_mem_resource,
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.mem_offset = 0x00000000,
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.io_resource = &sh7785_io_resource,
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.io_offset = 0x00000000,
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.io_map_base = SH7780_PCI_IO_BASE,
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};
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static int __init sh7780_pci_init(void)
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{
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struct pci_channel *chan = &sh7780_pci_controller;
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phys_addr_t memphys;
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size_t memsize;
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unsigned int id;
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const char *type;
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printk(KERN_NOTICE "PCI: Starting intialization.\n");
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chan->reg_base = 0xfe040000;
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/* Enable CPU access to the PCIC registers. */
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__raw_writel(PCIECR_ENBL, PCIECR);
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/* Reset */
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__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST,
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chan->reg_base + SH4_PCICR);
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/* Wait for it to come back up.. */
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mdelay(100);
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id = __raw_readw(chan->reg_base + PCI_VENDOR_ID);
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if (id != PCI_VENDOR_ID_RENESAS) {
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printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
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return -ENODEV;
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}
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id = __raw_readw(chan->reg_base + PCI_DEVICE_ID);
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type = (id == PCI_DEVICE_ID_RENESAS_SH7763) ? "SH7763" :
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(id == PCI_DEVICE_ID_RENESAS_SH7780) ? "SH7780" :
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(id == PCI_DEVICE_ID_RENESAS_SH7781) ? "SH7781" :
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(id == PCI_DEVICE_ID_RENESAS_SH7785) ? "SH7785" :
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NULL;
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if (unlikely(!type)) {
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printk(KERN_ERR "PCI: Found an unsupported Renesas host "
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"controller, device id 0x%04x.\n", id);
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return -EINVAL;
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}
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printk(KERN_NOTICE "PCI: Found a Renesas %s host "
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"controller, revision %d.\n", type,
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__raw_readb(chan->reg_base + PCI_REVISION_ID));
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/*
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* Now throw it in to register initialization mode and
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* start the real work.
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*/
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__raw_writel(SH4_PCICR_PREFIX, chan->reg_base + SH4_PCICR);
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memphys = __pa(memory_start);
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memsize = memory_end - memory_start;
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/*
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* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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*/
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__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
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__raw_writel(memphys, chan->reg_base + SH4_PCILAR0);
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__raw_writel((memsize - 1) << 9 | 1,
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chan->reg_base + SH4_PCILSR0);
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/* Clear out PCI arbiter IRQs */
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__raw_writel(0, chan->reg_base + SH4_PCIAINT);
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/* Unmask all of the arbiter IRQs. */
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__raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
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SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \
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SH4_PCIAINT_WDPE, chan->reg_base + SH4_PCIAINTM);
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/* Clear all error conditions */
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__raw_writew(PCI_STATUS_DETECTED_PARITY | \
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PCI_STATUS_SIG_SYSTEM_ERROR | \
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PCI_STATUS_REC_MASTER_ABORT | \
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PCI_STATUS_REC_TARGET_ABORT | \
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PCI_STATUS_SIG_TARGET_ABORT | \
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PCI_STATUS_PARITY, chan->reg_base + PCI_STATUS);
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__raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \
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PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
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PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
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/* Unmask all of the PCI IRQs */
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__raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
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SH4_PCIINTM_MDEIM | SH4_PCIINTM_APEDIM | \
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SH4_PCIINTM_SDIM | SH4_PCIINTM_DPEITWM | \
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SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM | \
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SH4_PCIINTM_MADIMM | SH4_PCIINTM_MWPDIM | \
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SH4_PCIINTM_MRDPEIM, chan->reg_base + SH4_PCIINTM);
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/*
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* Disable the cache snoop controller for non-coherent DMA.
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*/
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__raw_writel(0, chan->reg_base + SH7780_PCICSCR0);
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__raw_writel(0, chan->reg_base + SH7780_PCICSAR0);
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__raw_writel(0, chan->reg_base + SH7780_PCICSCR1);
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__raw_writel(0, chan->reg_base + SH7780_PCICSAR1);
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__raw_writel(0xfd000000, chan->reg_base + SH7780_PCIMBR0);
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__raw_writel(0x00fc0000, chan->reg_base + SH7780_PCIMBMR0);
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__raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
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__raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
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/*
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* Initialization mode complete, release the control register and
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* enable round robin mode to stop device overruns/starvation.
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*/
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__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO,
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chan->reg_base + SH4_PCICR);
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register_pci_controller(chan);
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return 0;
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}
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arch_initcall(sh7780_pci_init);
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