4089caa7d0
For most OCTEON SoCs there is a repeated and redundant register definition for almost every hardware register, although the register bit fields would not differ from other SoCs. Since the driver code should use only one definition for simplicity, these other fields are just redundant and can be deleted. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org
172 lines
4.0 KiB
C
172 lines
4.0 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_RNM_DEFS_H__
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#define __CVMX_RNM_DEFS_H__
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#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
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#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
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#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
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#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
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#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
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union cvmx_rnm_bist_status {
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uint64_t u64;
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struct cvmx_rnm_bist_status_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_2_63:62;
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uint64_t rrc:1;
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uint64_t mem:1;
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#else
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uint64_t mem:1;
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uint64_t rrc:1;
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uint64_t reserved_2_63:62;
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#endif
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} s;
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};
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union cvmx_rnm_ctl_status {
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uint64_t u64;
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struct cvmx_rnm_ctl_status_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_12_63:52;
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uint64_t dis_mak:1;
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uint64_t eer_lck:1;
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uint64_t eer_val:1;
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uint64_t ent_sel:4;
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uint64_t exp_ent:1;
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uint64_t rng_rst:1;
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uint64_t rnm_rst:1;
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uint64_t rng_en:1;
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uint64_t ent_en:1;
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#else
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uint64_t ent_en:1;
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uint64_t rng_en:1;
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uint64_t rnm_rst:1;
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uint64_t rng_rst:1;
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uint64_t exp_ent:1;
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uint64_t ent_sel:4;
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uint64_t eer_val:1;
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uint64_t eer_lck:1;
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uint64_t dis_mak:1;
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uint64_t reserved_12_63:52;
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#endif
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} s;
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struct cvmx_rnm_ctl_status_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_4_63:60;
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uint64_t rng_rst:1;
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uint64_t rnm_rst:1;
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uint64_t rng_en:1;
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uint64_t ent_en:1;
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#else
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uint64_t ent_en:1;
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uint64_t rng_en:1;
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uint64_t rnm_rst:1;
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uint64_t rng_rst:1;
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uint64_t reserved_4_63:60;
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#endif
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} cn30xx;
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struct cvmx_rnm_ctl_status_cn50xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_9_63:55;
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uint64_t ent_sel:4;
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uint64_t exp_ent:1;
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uint64_t rng_rst:1;
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uint64_t rnm_rst:1;
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uint64_t rng_en:1;
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uint64_t ent_en:1;
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#else
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uint64_t ent_en:1;
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uint64_t rng_en:1;
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uint64_t rnm_rst:1;
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uint64_t rng_rst:1;
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uint64_t exp_ent:1;
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uint64_t ent_sel:4;
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uint64_t reserved_9_63:55;
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#endif
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} cn50xx;
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struct cvmx_rnm_ctl_status_cn63xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_11_63:53;
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uint64_t eer_lck:1;
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uint64_t eer_val:1;
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uint64_t ent_sel:4;
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uint64_t exp_ent:1;
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uint64_t rng_rst:1;
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uint64_t rnm_rst:1;
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uint64_t rng_en:1;
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uint64_t ent_en:1;
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#else
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uint64_t ent_en:1;
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uint64_t rng_en:1;
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uint64_t rnm_rst:1;
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uint64_t rng_rst:1;
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uint64_t exp_ent:1;
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uint64_t ent_sel:4;
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uint64_t eer_val:1;
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uint64_t eer_lck:1;
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uint64_t reserved_11_63:53;
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#endif
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} cn63xx;
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};
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union cvmx_rnm_eer_dbg {
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uint64_t u64;
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struct cvmx_rnm_eer_dbg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t dat:64;
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#else
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uint64_t dat:64;
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#endif
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} s;
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};
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union cvmx_rnm_eer_key {
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uint64_t u64;
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struct cvmx_rnm_eer_key_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t key:64;
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#else
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uint64_t key:64;
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#endif
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} s;
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};
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union cvmx_rnm_serial_num {
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uint64_t u64;
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struct cvmx_rnm_serial_num_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t dat:64;
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#else
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uint64_t dat:64;
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#endif
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} s;
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};
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#endif
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