39bd2b6a37
The 'phandle-array' type is a bit ambiguous. It can be either just an
array of phandles or an array of phandles plus args. Many schemas for
phandle-array properties aren't clear in the schema which case applies
though the description usually describes it.
The array of phandles case boils down to needing:
items:
maxItems: 1
The phandle plus args cases should typically take this form:
items:
- items:
- description: A phandle
- description: 1st arg cell
- description: 2nd arg cell
With this change, some examples need updating so that the bracketing of
property values matches the schema.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20220119015038.2433585-1-robh@kernel.org
48 lines
1.3 KiB
YAML
48 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
# Copyright 2021 Arm Ltd.
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
|
|
|
|
maintainers:
|
|
- Suzuki K Poulose <suzuki.poulose@arm.com>
|
|
- Robin Murphy <robin.murphy@arm.com>
|
|
|
|
description:
|
|
ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
|
|
L3 memory system, control logic and external interfaces to form a multicore
|
|
cluster. The PMU enables gathering various statistics on the operation of the
|
|
DSU. The PMU provides independent 32-bit counters that can count any of the
|
|
supported events, along with a 64-bit cycle counter. The PMU is accessed via
|
|
CPU system registers and has no MMIO component.
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- const: arm,dsu-pmu
|
|
- items:
|
|
- const: arm,dsu-110-pmu
|
|
- const: arm,dsu-pmu
|
|
|
|
interrupts:
|
|
items:
|
|
- description: nCLUSTERPMUIRQ interrupt
|
|
|
|
cpus:
|
|
$ref: /schemas/types.yaml#/definitions/phandle-array
|
|
minItems: 1
|
|
maxItems: 12
|
|
items:
|
|
maxItems: 1
|
|
description: List of phandles for the CPUs connected to this DSU instance.
|
|
|
|
required:
|
|
- compatible
|
|
- interrupts
|
|
- cpus
|
|
|
|
additionalProperties: false
|