6a6eff73a9
Add a driver that handles the different NoCs found on SM6350, generated from the downstream dtb. We're exluding ALC, IP0 and all _display nodes. ALC will not be voted from the kernel[1] and IP0 is handled by the clk-rpmh driver[2]. [1] https://lore.kernel.org/linux-arm-msm/1e79c73f22c8891dc9f868babd940fca@codeaurora.org/ [2] https://lore.kernel.org/linux-arm-msm/20220412220033.1273607-1-swboyd@chromium.org/ Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20220525144404.200390-5-luca.weiss@fairphone.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
140 lines
4.8 KiB
C
140 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Qualcomm #define SM6350 interconnect IDs
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*
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* Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SM6350_H
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#define __DRIVERS_INTERCONNECT_QCOM_SM6350_H
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#define SM6350_A1NOC_SNOC_MAS 0
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#define SM6350_A1NOC_SNOC_SLV 1
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#define SM6350_A2NOC_SNOC_MAS 2
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#define SM6350_A2NOC_SNOC_SLV 3
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#define SM6350_MASTER_A1NOC_CFG 4
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#define SM6350_MASTER_A2NOC_CFG 5
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#define SM6350_MASTER_AMPSS_M0 6
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#define SM6350_MASTER_CAMNOC_HF 7
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#define SM6350_MASTER_CAMNOC_HF0_UNCOMP 8
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#define SM6350_MASTER_CAMNOC_ICP 9
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#define SM6350_MASTER_CAMNOC_ICP_UNCOMP 10
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#define SM6350_MASTER_CAMNOC_SF 11
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#define SM6350_MASTER_CAMNOC_SF_UNCOMP 12
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#define SM6350_MASTER_CNOC_DC_NOC 13
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#define SM6350_MASTER_CNOC_MNOC_CFG 14
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#define SM6350_MASTER_COMPUTE_NOC 15
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#define SM6350_MASTER_CRYPTO_CORE_0 16
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#define SM6350_MASTER_EMMC 17
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#define SM6350_MASTER_GEM_NOC_CFG 18
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#define SM6350_MASTER_GEM_NOC_SNOC 19
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#define SM6350_MASTER_GIC 20
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#define SM6350_MASTER_GRAPHICS_3D 21
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#define SM6350_MASTER_IPA 22
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#define SM6350_MASTER_LLCC 23
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#define SM6350_MASTER_MDP_PORT0 24
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#define SM6350_MASTER_MNOC_HF_MEM_NOC 25
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#define SM6350_MASTER_MNOC_SF_MEM_NOC 26
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#define SM6350_MASTER_NPU 27
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#define SM6350_MASTER_NPU_NOC_CFG 28
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#define SM6350_MASTER_NPU_PROC 29
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#define SM6350_MASTER_NPU_SYS 30
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#define SM6350_MASTER_PIMEM 31
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#define SM6350_MASTER_QDSS_BAM 32
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#define SM6350_MASTER_QDSS_DAP 33
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#define SM6350_MASTER_QDSS_ETR 34
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#define SM6350_MASTER_QUP_0 35
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#define SM6350_MASTER_QUP_1 36
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#define SM6350_MASTER_QUP_CORE_0 37
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#define SM6350_MASTER_QUP_CORE_1 38
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#define SM6350_MASTER_SDCC_2 39
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#define SM6350_MASTER_SNOC_CFG 40
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#define SM6350_MASTER_SNOC_GC_MEM_NOC 41
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#define SM6350_MASTER_SNOC_SF_MEM_NOC 42
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#define SM6350_MASTER_SYS_TCU 43
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#define SM6350_MASTER_UFS_MEM 44
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#define SM6350_MASTER_USB3 45
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#define SM6350_MASTER_VIDEO_P0 46
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#define SM6350_MASTER_VIDEO_PROC 47
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#define SM6350_SLAVE_A1NOC_CFG 48
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#define SM6350_SLAVE_A2NOC_CFG 49
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#define SM6350_SLAVE_AHB2PHY 50
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#define SM6350_SLAVE_AHB2PHY_2 51
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#define SM6350_SLAVE_AOSS 52
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#define SM6350_SLAVE_APPSS 53
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#define SM6350_SLAVE_BOOT_ROM 54
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#define SM6350_SLAVE_CAMERA_CFG 55
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#define SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG 56
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#define SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG 57
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#define SM6350_SLAVE_CAMNOC_UNCOMP 58
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#define SM6350_SLAVE_CDSP_GEM_NOC 59
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#define SM6350_SLAVE_CLK_CTL 60
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#define SM6350_SLAVE_CNOC_DDRSS 61
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#define SM6350_SLAVE_CNOC_MNOC_CFG 62
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#define SM6350_SLAVE_CNOC_MSS 63
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#define SM6350_SLAVE_CRYPTO_0_CFG 64
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#define SM6350_SLAVE_DCC_CFG 65
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#define SM6350_SLAVE_DISPLAY_CFG 66
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#define SM6350_SLAVE_DISPLAY_THROTTLE_CFG 67
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#define SM6350_SLAVE_EBI_CH0 68
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#define SM6350_SLAVE_EMMC_CFG 69
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#define SM6350_SLAVE_GEM_NOC_CFG 70
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#define SM6350_SLAVE_GEM_NOC_SNOC 71
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#define SM6350_SLAVE_GLM 72
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#define SM6350_SLAVE_GRAPHICS_3D_CFG 73
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#define SM6350_SLAVE_IMEM_CFG 74
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#define SM6350_SLAVE_IPA_CFG 75
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#define SM6350_SLAVE_ISENSE_CFG 76
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#define SM6350_SLAVE_LLCC 77
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#define SM6350_SLAVE_LLCC_CFG 78
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#define SM6350_SLAVE_MCDMA_MS_MPU_CFG 79
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#define SM6350_SLAVE_MNOC_HF_MEM_NOC 80
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#define SM6350_SLAVE_MNOC_SF_MEM_NOC 81
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#define SM6350_SLAVE_MSS_PROC_MS_MPU_CFG 82
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#define SM6350_SLAVE_NPU_CAL_DP0 83
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#define SM6350_SLAVE_NPU_CFG 84
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#define SM6350_SLAVE_NPU_COMPUTE_NOC 85
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#define SM6350_SLAVE_NPU_CP 86
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#define SM6350_SLAVE_NPU_DPM 87
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#define SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG 88
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#define SM6350_SLAVE_NPU_LLM_CFG 89
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#define SM6350_SLAVE_NPU_TCM 90
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#define SM6350_SLAVE_OCIMEM 91
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#define SM6350_SLAVE_PDM 92
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#define SM6350_SLAVE_PIMEM 93
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#define SM6350_SLAVE_PIMEM_CFG 94
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#define SM6350_SLAVE_PRNG 95
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#define SM6350_SLAVE_QDSS_CFG 96
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#define SM6350_SLAVE_QDSS_STM 97
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#define SM6350_SLAVE_QM_CFG 98
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#define SM6350_SLAVE_QM_MPU_CFG 99
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#define SM6350_SLAVE_QUP_0 100
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#define SM6350_SLAVE_QUP_1 101
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#define SM6350_SLAVE_QUP_CORE_0 102
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#define SM6350_SLAVE_QUP_CORE_1 103
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#define SM6350_SLAVE_RBCPR_CX_CFG 104
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#define SM6350_SLAVE_RBCPR_MX_CFG 105
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#define SM6350_SLAVE_SDCC_2 106
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#define SM6350_SLAVE_SECURITY 107
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#define SM6350_SLAVE_SERVICE_A1NOC 108
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#define SM6350_SLAVE_SERVICE_A2NOC 109
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#define SM6350_SLAVE_SERVICE_CNOC 110
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#define SM6350_SLAVE_SERVICE_GEM_NOC 111
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#define SM6350_SLAVE_SERVICE_MNOC 112
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#define SM6350_SLAVE_SERVICE_NPU_NOC 113
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#define SM6350_SLAVE_SERVICE_SNOC 114
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#define SM6350_SLAVE_SNOC_CFG 115
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#define SM6350_SLAVE_SNOC_GEM_NOC_GC 116
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#define SM6350_SLAVE_SNOC_GEM_NOC_SF 117
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#define SM6350_SLAVE_TCSR 118
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#define SM6350_SLAVE_TCU 119
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#define SM6350_SLAVE_UFS_MEM_CFG 120
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#define SM6350_SLAVE_USB3 121
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#define SM6350_SLAVE_VENUS_CFG 122
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#define SM6350_SLAVE_VENUS_THROTTLE_CFG 123
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#define SM6350_SLAVE_VSENSE_CTRL_CFG 124
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#define SM6350_SNOC_CNOC_MAS 125
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#define SM6350_SNOC_CNOC_SLV 126
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#endif
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