a912e80bd0
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 675 mass ave cambridge ma 02139 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 35 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.655028468@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
|
|
* JZ4740 IRQ definitions
|
|
*/
|
|
|
|
#ifndef __ASM_MACH_JZ4740_IRQ_H__
|
|
#define __ASM_MACH_JZ4740_IRQ_H__
|
|
|
|
#define MIPS_CPU_IRQ_BASE 0
|
|
#define JZ4740_IRQ_BASE 8
|
|
|
|
#ifdef CONFIG_MACH_JZ4740
|
|
# define NR_INTC_IRQS 32
|
|
#else
|
|
# define NR_INTC_IRQS 64
|
|
#endif
|
|
|
|
/* 1st-level interrupts */
|
|
#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
|
|
#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
|
|
#define JZ4740_IRQ_UHC JZ4740_IRQ(3)
|
|
#define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
|
|
#define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
|
|
#define JZ4740_IRQ_SADC JZ4740_IRQ(12)
|
|
#define JZ4740_IRQ_MSC JZ4740_IRQ(14)
|
|
#define JZ4740_IRQ_RTC JZ4740_IRQ(15)
|
|
#define JZ4740_IRQ_SSI JZ4740_IRQ(16)
|
|
#define JZ4740_IRQ_CIM JZ4740_IRQ(17)
|
|
#define JZ4740_IRQ_AIC JZ4740_IRQ(18)
|
|
#define JZ4740_IRQ_ETH JZ4740_IRQ(19)
|
|
#define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
|
|
#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
|
|
#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
|
|
#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
|
|
#define JZ4740_IRQ_UDC JZ4740_IRQ(24)
|
|
#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
|
|
#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
|
|
#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
|
|
#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
|
|
#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
|
|
#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
|
|
|
|
#define JZ4780_IRQ_TCU2 JZ4740_IRQ(25)
|
|
|
|
/* 2nd-level interrupts */
|
|
#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(NR_INTC_IRQS) + (x))
|
|
|
|
#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
|
|
#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(NR_INTC_IRQS + 16) + (x))
|
|
|
|
#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(NR_INTC_IRQS + 144)
|
|
|
|
#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
|
|
|
|
#endif
|