3b3397e203
The function meson_gxl_read_status is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'meson_gxl_read_status' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
154 lines
4.4 KiB
C
154 lines
4.4 KiB
C
/*
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* Amlogic Meson GXL Internal PHY Driver
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*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2016 BayLibre, SAS. All rights reserved.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/bitfield.h>
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static int meson_gxl_config_init(struct phy_device *phydev)
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{
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/* Enable Analog and DSP register Bank access by */
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x14, 0x0400);
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x14, 0x0400);
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/* Write Analog register 23 */
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phy_write(phydev, 0x17, 0x8E0D);
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phy_write(phydev, 0x14, 0x4417);
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/* Enable fractional PLL */
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phy_write(phydev, 0x17, 0x0005);
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phy_write(phydev, 0x14, 0x5C1B);
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, 0x17, 0x029A);
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phy_write(phydev, 0x14, 0x5C1D);
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, 0x17, 0xAAAA);
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phy_write(phydev, 0x14, 0x5C1C);
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return 0;
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}
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/* This function is provided to cope with the possible failures of this phy
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* during aneg process. When aneg fails, the PHY reports that aneg is done
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* but the value found in MII_LPA is wrong:
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* - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
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* the link partner (LP) supports aneg but the LP never acked our base
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* code word, it is likely that we never sent it to begin with.
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* - Late failures: MII_LPA is filled with a value which seems to make sense
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* but it actually is not what the LP is advertising. It seems that we
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* can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
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* If this particular bit is not set when aneg is reported being done,
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* it means MII_LPA is likely to be wrong.
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*
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* In both case, forcing a restart of the aneg process solve the problem.
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* When this failure happens, the first retry is usually successful but,
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* in some cases, it may take up to 6 retries to get a decent result
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*/
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static int meson_gxl_read_status(struct phy_device *phydev)
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{
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int ret, wol, lpa, exp;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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ret = genphy_aneg_done(phydev);
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if (ret < 0)
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return ret;
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else if (!ret)
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goto read_status_continue;
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/* Need to access WOL bank, make sure the access is open */
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ret = phy_write(phydev, 0x14, 0x0000);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0000);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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if (ret)
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return ret;
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/* Request LPI_STATUS WOL register */
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ret = phy_write(phydev, 0x14, 0x8D80);
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if (ret)
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return ret;
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/* Read LPI_STATUS value */
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wol = phy_read(phydev, 0x15);
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if (wol < 0)
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return wol;
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lpa = phy_read(phydev, MII_LPA);
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if (lpa < 0)
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return lpa;
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exp = phy_read(phydev, MII_EXPANSION);
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if (exp < 0)
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return exp;
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if (!(wol & BIT(12)) ||
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((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
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/* Looks like aneg failed after all */
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phydev_dbg(phydev, "LPA corruption - aneg restart\n");
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return genphy_restart_aneg(phydev);
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}
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}
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read_status_continue:
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return genphy_read_status(phydev);
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}
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static struct phy_driver meson_gxl_phy[] = {
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{
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.phy_id = 0x01814400,
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.phy_id_mask = 0xfffffff0,
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.name = "Meson GXL Internal PHY",
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.features = PHY_BASIC_FEATURES,
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.flags = PHY_IS_INTERNAL,
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.config_init = meson_gxl_config_init,
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.config_aneg = genphy_config_aneg,
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.aneg_done = genphy_aneg_done,
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.read_status = meson_gxl_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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};
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static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
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{ 0x01814400, 0xfffffff0 },
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{ }
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};
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module_phy_driver(meson_gxl_phy);
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MODULE_DEVICE_TABLE(mdio, meson_gxl_tbl);
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MODULE_DESCRIPTION("Amlogic Meson GXL Internal PHY driver");
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MODULE_AUTHOR("Baoqi wang");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_LICENSE("GPL");
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