linux/drivers/clk/socfpga
Dinh Nguyen 3b5015c4d8 clk: socfpga: stratix10: add additional clocks needed for the NAND IP
The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:36:56 -07:00
..
clk-gate-a10.c clk: socfpga: Fix the smplsel on Arria10 and Stratix10 2017-06-19 17:01:55 -07:00
clk-gate-s10.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-gate.c clk: socfpga: Don't have get_parent for single parent ops 2019-01-24 11:36:25 -08:00
clk-periph-a10.c clk: socfpga: allow for multiple parents on Arria10 periph clocks 2016-02-22 14:17:37 -08:00
clk-periph-s10.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-periph.c clk: socfpga: Add a second parent option for the dbg_base_clk 2015-08-24 16:49:03 -07:00
clk-pll-a10.c clk: socfpga: fix refcount leak 2018-12-28 11:29:06 -08:00
clk-pll-s10.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-pll.c clk: socfpga: fix refcount leak 2018-12-28 11:29:06 -08:00
clk-s10.c clk: socfpga: stratix10: add additional clocks needed for the NAND IP 2019-06-25 14:36:56 -07:00
clk.c clk: socfpga: add a clock driver for the Arria 10 platform 2015-05-21 15:16:04 -07:00
clk.h clk: socfpga: stratix10: add clock driver for Stratix10 platform 2018-04-06 10:12:35 -07:00
Makefile clk: socfpga: stratix10: add clock driver for Stratix10 platform 2018-04-06 10:12:35 -07:00
stratix10-clk.h clk: socfpga: stratix10: add clock driver for Stratix10 platform 2018-04-06 10:12:35 -07:00