3bb6ce6686
Thus far we've tried to carefully work around the fact that old userspace relied on the AGP-backed legacy buffer mapping ioctls for a bit too long. But it's really horribly, and now some new users for it started to show up again: http://www.mail-archive.com/mesa-dev@lists.freedesktop.org/msg45547.html This uses drmAgpSize to figure out the GTT size, which is both the wrong thing to inquire and also might force us to keep this crap around for another few years. So I want to stop this particular zombie from raising ever again. Now it's only been 4 years since XvMC was fixed for gen3, so a bit early by the usual rules. But since Linus explicitly said that an ABI breakage only counts if someone actually observes it I want to tempt fate an accelarate the demise of AGP. We probably need to wait 2-3 kernel releases with this shipping until we go on a killing spree code-wise. v2: Remove intel_agp_enabled since it's unused (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dave Airlie <airlied@gmail.com> Acked-by: Dave Airlie <airlied@gmail.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
933 lines
28 KiB
C
933 lines
28 KiB
C
/*
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* Intel AGPGART routines.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/pagemap.h>
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#include <linux/agp_backend.h>
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#include <asm/smp.h>
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#include "agp.h"
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#include "intel-agp.h"
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#include <drm/intel-gtt.h>
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static int intel_fetch_size(void)
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{
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int i;
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u16 temp;
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struct aper_size_info_16 *values;
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pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
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values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static int __intel_8xx_fetch_size(u8 temp)
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{
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int i;
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struct aper_size_info_8 *values;
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values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static int intel_8xx_fetch_size(void)
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{
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u8 temp;
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pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
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return __intel_8xx_fetch_size(temp);
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}
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static int intel_815_fetch_size(void)
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{
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u8 temp;
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/* Intel 815 chipsets have a _weird_ APSIZE register with only
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* one non-reserved bit, so mask the others out ... */
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pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
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temp &= (1 << 3);
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return __intel_8xx_fetch_size(temp);
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}
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static void intel_tlbflush(struct agp_memory *mem)
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{
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
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}
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static void intel_8xx_tlbflush(struct agp_memory *mem)
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{
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u32 temp;
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pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
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pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
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}
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static void intel_cleanup(void)
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{
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u16 temp;
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struct aper_size_info_16 *previous_size;
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previous_size = A_SIZE_16(agp_bridge->previous_size);
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
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pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
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}
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static void intel_8xx_cleanup(void)
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{
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u16 temp;
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struct aper_size_info_8 *previous_size;
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previous_size = A_SIZE_8(agp_bridge->previous_size);
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
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}
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static int intel_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_16 *current_size;
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current_size = A_SIZE_16(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
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/* paccfg/nbxcfg */
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
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(temp2 & ~(1 << 10)) | (1 << 9));
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/* clear any possible error conditions */
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pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
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return 0;
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}
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static int intel_815_configure(void)
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{
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u32 temp, addr;
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u8 temp2;
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struct aper_size_info_8 *current_size;
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/* attbase - aperture base */
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/* the Intel 815 chipset spec. says that bits 29-31 in the
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* ATTBASE register are reserved -> try not to write them */
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if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
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dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
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return -EINVAL;
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}
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
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current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
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addr &= INTEL_815_ATTBASE_MASK;
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addr |= agp_bridge->gatt_bus_addr;
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* apcont */
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pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
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pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
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/* clear any possible error conditions */
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/* Oddness : this chipset seems to have no ERRSTS register ! */
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return 0;
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}
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static void intel_820_tlbflush(struct agp_memory *mem)
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{
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return;
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}
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static void intel_820_cleanup(void)
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{
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u8 temp;
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struct aper_size_info_8 *previous_size;
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previous_size = A_SIZE_8(agp_bridge->previous_size);
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pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
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pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
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temp & ~(1 << 1));
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
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previous_size->size_value);
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}
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static int intel_820_configure(void)
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{
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u32 temp;
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u8 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* global enable aperture access */
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/* This flag is not accessed through MCHCFG register as in */
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/* i850 chipset. */
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pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
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pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
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/* clear any possible AGP-related error conditions */
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pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
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return 0;
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}
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static int intel_840_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* mcgcfg */
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pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
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pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
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/* clear any possible error conditions */
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pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
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return 0;
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}
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static int intel_845_configure(void)
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{
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u32 temp;
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u8 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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if (agp_bridge->apbase_config != 0) {
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pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
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agp_bridge->apbase_config);
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} else {
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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agp_bridge->apbase_config = temp;
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}
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* agpm */
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pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
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pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
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/* clear any possible error conditions */
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pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
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return 0;
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}
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static int intel_850_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* mcgcfg */
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pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
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pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
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/* clear any possible AGP-related error conditions */
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pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
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return 0;
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}
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static int intel_860_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* mcgcfg */
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pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
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pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
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/* clear any possible AGP-related error conditions */
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pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
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return 0;
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}
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static int intel_830mp_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* gmch */
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
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/* clear any possible AGP-related error conditions */
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pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
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return 0;
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}
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static int intel_7505_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture base */
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pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
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/* mchcfg */
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pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
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pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
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return 0;
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}
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/* Setup function */
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static const struct gatt_mask intel_generic_masks[] =
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{
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{.mask = 0x00000017, .type = 0}
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};
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static const struct aper_size_info_8 intel_815_sizes[2] =
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{
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{64, 16384, 4, 0},
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{32, 8192, 3, 8},
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};
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static const struct aper_size_info_8 intel_8xx_sizes[7] =
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{
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{256, 65536, 6, 0},
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{128, 32768, 5, 32},
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{64, 16384, 4, 48},
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{32, 8192, 3, 56},
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{16, 4096, 2, 60},
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{8, 2048, 1, 62},
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{4, 1024, 0, 63}
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};
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static const struct aper_size_info_16 intel_generic_sizes[7] =
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{
|
|
{256, 65536, 6, 0},
|
|
{128, 32768, 5, 32},
|
|
{64, 16384, 4, 48},
|
|
{32, 8192, 3, 56},
|
|
{16, 4096, 2, 60},
|
|
{8, 2048, 1, 62},
|
|
{4, 1024, 0, 63}
|
|
};
|
|
|
|
static const struct aper_size_info_8 intel_830mp_sizes[4] =
|
|
{
|
|
{256, 65536, 6, 0},
|
|
{128, 32768, 5, 32},
|
|
{64, 16384, 4, 48},
|
|
{32, 8192, 3, 56}
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_generic_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_generic_sizes,
|
|
.size_type = U16_APER_SIZE,
|
|
.num_aperture_sizes = 7,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_configure,
|
|
.fetch_size = intel_fetch_size,
|
|
.cleanup = intel_cleanup,
|
|
.tlb_flush = intel_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_815_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_815_sizes,
|
|
.size_type = U8_APER_SIZE,
|
|
.num_aperture_sizes = 2,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_815_configure,
|
|
.fetch_size = intel_815_fetch_size,
|
|
.cleanup = intel_8xx_cleanup,
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_820_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
.size_type = U8_APER_SIZE,
|
|
.num_aperture_sizes = 7,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_820_configure,
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
.cleanup = intel_820_cleanup,
|
|
.tlb_flush = intel_820_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_830mp_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_830mp_sizes,
|
|
.size_type = U8_APER_SIZE,
|
|
.num_aperture_sizes = 4,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_830mp_configure,
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
.cleanup = intel_8xx_cleanup,
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_840_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
.size_type = U8_APER_SIZE,
|
|
.num_aperture_sizes = 7,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_840_configure,
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
.cleanup = intel_8xx_cleanup,
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_845_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
.size_type = U8_APER_SIZE,
|
|
.num_aperture_sizes = 7,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_845_configure,
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
.cleanup = intel_8xx_cleanup,
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_850_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
.size_type = U8_APER_SIZE,
|
|
.num_aperture_sizes = 7,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_850_configure,
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
.cleanup = intel_8xx_cleanup,
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_860_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
.size_type = U8_APER_SIZE,
|
|
.num_aperture_sizes = 7,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_860_configure,
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
.cleanup = intel_8xx_cleanup,
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
static const struct agp_bridge_driver intel_7505_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
.size_type = U8_APER_SIZE,
|
|
.num_aperture_sizes = 7,
|
|
.needs_scratch_page = true,
|
|
.configure = intel_7505_configure,
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
.cleanup = intel_8xx_cleanup,
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = intel_generic_masks,
|
|
.agp_enable = agp_generic_enable,
|
|
.cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
.free_gatt_table = agp_generic_free_gatt_table,
|
|
.insert_memory = agp_generic_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
};
|
|
|
|
/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
|
|
* driver and gmch_driver must be non-null, and find_gmch will determine
|
|
* which one should be used if a gmch_chip_id is present.
|
|
*/
|
|
static const struct intel_agp_driver_description {
|
|
unsigned int chip_id;
|
|
char *name;
|
|
const struct agp_bridge_driver *driver;
|
|
} intel_agp_chipsets[] = {
|
|
{ PCI_DEVICE_ID_INTEL_82443LX_0, "440LX", &intel_generic_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82443BX_0, "440BX", &intel_generic_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82443GX_0, "440GX", &intel_generic_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82815_MC, "i815", &intel_815_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82820_HB, "i820", &intel_820_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82820_UP_HB, "i820", &intel_820_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82830_HB, "830M", &intel_830mp_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82840_HB, "i840", &intel_840_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82845_HB, "i845", &intel_845_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82845G_HB, "845G", &intel_845_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82850_HB, "i850", &intel_850_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82854_HB, "854", &intel_845_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82855PM_HB, "855PM", &intel_845_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82855GM_HB, "855GM", &intel_845_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82860_HB, "i860", &intel_860_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82865_HB, "865", &intel_845_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82875_HB, "i875", &intel_845_driver },
|
|
{ PCI_DEVICE_ID_INTEL_7505_0, "E7505", &intel_7505_driver },
|
|
{ PCI_DEVICE_ID_INTEL_7205_0, "E7205", &intel_7505_driver },
|
|
{ 0, NULL, NULL }
|
|
};
|
|
|
|
static int agp_intel_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct agp_bridge_data *bridge;
|
|
u8 cap_ptr = 0;
|
|
struct resource *r;
|
|
int i, err;
|
|
|
|
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
|
|
|
|
bridge = agp_alloc_bridge();
|
|
if (!bridge)
|
|
return -ENOMEM;
|
|
|
|
bridge->capndx = cap_ptr;
|
|
|
|
if (intel_gmch_probe(pdev, NULL, bridge))
|
|
goto found_gmch;
|
|
|
|
for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
|
|
/* In case that multiple models of gfx chip may
|
|
stand on same host bridge type, this can be
|
|
sure we detect the right IGD. */
|
|
if (pdev->device == intel_agp_chipsets[i].chip_id) {
|
|
bridge->driver = intel_agp_chipsets[i].driver;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!bridge->driver) {
|
|
if (cap_ptr)
|
|
dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
|
|
pdev->vendor, pdev->device);
|
|
agp_put_bridge(bridge);
|
|
return -ENODEV;
|
|
}
|
|
|
|
bridge->dev = pdev;
|
|
bridge->dev_private_data = NULL;
|
|
|
|
dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
|
|
|
|
/*
|
|
* The following fixes the case where the BIOS has "forgotten" to
|
|
* provide an address range for the GART.
|
|
* 20030610 - hamish@zot.org
|
|
* This happens before pci_enable_device() intentionally;
|
|
* calling pci_enable_device() before assigning the resource
|
|
* will result in the GART being disabled on machines with such
|
|
* BIOSs (the GART ends up with a BAR starting at 0, which
|
|
* conflicts a lot of other devices).
|
|
*/
|
|
r = &pdev->resource[0];
|
|
if (!r->start && r->end) {
|
|
if (pci_assign_resource(pdev, 0)) {
|
|
dev_err(&pdev->dev, "can't assign resource 0\n");
|
|
agp_put_bridge(bridge);
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* If the device has not been properly setup, the following will catch
|
|
* the problem and should stop the system from crashing.
|
|
* 20030610 - hamish@zot.org
|
|
*/
|
|
if (pci_enable_device(pdev)) {
|
|
dev_err(&pdev->dev, "can't enable PCI device\n");
|
|
agp_put_bridge(bridge);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Fill in the mode register */
|
|
if (cap_ptr) {
|
|
pci_read_config_dword(pdev,
|
|
bridge->capndx+PCI_AGP_STATUS,
|
|
&bridge->mode);
|
|
}
|
|
|
|
found_gmch:
|
|
pci_set_drvdata(pdev, bridge);
|
|
err = agp_add_bridge(bridge);
|
|
return err;
|
|
}
|
|
|
|
static void agp_intel_remove(struct pci_dev *pdev)
|
|
{
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
agp_remove_bridge(bridge);
|
|
|
|
intel_gmch_remove();
|
|
|
|
agp_put_bridge(bridge);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int agp_intel_resume(struct pci_dev *pdev)
|
|
{
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
bridge->driver->configure();
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static struct pci_device_id agp_intel_pci_table[] = {
|
|
#define ID(x) \
|
|
{ \
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8), \
|
|
.class_mask = ~0, \
|
|
.vendor = PCI_VENDOR_ID_INTEL, \
|
|
.device = x, \
|
|
.subvendor = PCI_ANY_ID, \
|
|
.subdevice = PCI_ANY_ID, \
|
|
}
|
|
ID(PCI_DEVICE_ID_INTEL_82441), /* for HAS2 support */
|
|
ID(PCI_DEVICE_ID_INTEL_82443LX_0),
|
|
ID(PCI_DEVICE_ID_INTEL_82443BX_0),
|
|
ID(PCI_DEVICE_ID_INTEL_82443GX_0),
|
|
ID(PCI_DEVICE_ID_INTEL_82810_MC1),
|
|
ID(PCI_DEVICE_ID_INTEL_82810_MC3),
|
|
ID(PCI_DEVICE_ID_INTEL_82810E_MC),
|
|
ID(PCI_DEVICE_ID_INTEL_82815_MC),
|
|
ID(PCI_DEVICE_ID_INTEL_82820_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82830_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82840_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82845_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82845G_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82850_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82854_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82860_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82865_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82875_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_7505_0),
|
|
ID(PCI_DEVICE_ID_INTEL_7205_0),
|
|
ID(PCI_DEVICE_ID_INTEL_E7221_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82915G_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82945G_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82G35_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82965G_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_G33_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_Q35_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_Q33_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_GM45_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_Q45_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_G45_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_G41_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_B43_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
|
|
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
|
|
|
|
static struct pci_driver agp_intel_pci_driver = {
|
|
.name = "agpgart-intel",
|
|
.id_table = agp_intel_pci_table,
|
|
.probe = agp_intel_probe,
|
|
.remove = agp_intel_remove,
|
|
#ifdef CONFIG_PM
|
|
.resume = agp_intel_resume,
|
|
#endif
|
|
};
|
|
|
|
static int __init agp_intel_init(void)
|
|
{
|
|
if (agp_off)
|
|
return -EINVAL;
|
|
return pci_register_driver(&agp_intel_pci_driver);
|
|
}
|
|
|
|
static void __exit agp_intel_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&agp_intel_pci_driver);
|
|
}
|
|
|
|
module_init(agp_intel_init);
|
|
module_exit(agp_intel_cleanup);
|
|
|
|
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|
|
MODULE_LICENSE("GPL and additional rights");
|