3c4f2120d8
Logical Context is actually a big batch buffer consisting of multiple LRI commands + saved registers. It comprises Ring Context (the first 0x50 dwords) and Engine Context. The registers defined in Engine Context are command accessible, and safe to execute in VM Context. This patch 1. stops copy Ring Context and only copys Engine Context from VM Context 2. audits VM Engine Contexts to disallow undesired LRIs (if accessing registers out of Engine Context that hardware generates). Cc: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Wang Zhi <zhi.a.wang@intel.com> Signed-off-by: Yan Zhao <yan.y.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20201223034500.16983-1-yan.y.zhao@intel.com Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
58 lines
2.0 KiB
C
58 lines
2.0 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Ke Yu
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* Kevin Tian <kevin.tian@intel.com>
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* Zhiyuan Lv <zhiyuan.lv@intel.com>
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*
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* Contributors:
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* Min He <min.he@intel.com>
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* Ping Gao <ping.a.gao@intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Yulei Zhang <yulei.zhang@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#ifndef _GVT_CMD_PARSER_H_
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#define _GVT_CMD_PARSER_H_
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#define GVT_CMD_HASH_BITS 7
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struct intel_gvt;
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struct intel_shadow_wa_ctx;
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struct intel_vgpu_workload;
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void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
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int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
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int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload);
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int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx);
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void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu);
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int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload);
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#endif
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