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3cc2c646be
linux/drivers/net/phy/mscc
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Bjarni Jonasson 3cc2c646be net: phy: mscc: adding LCPLL reset to VSC8514 
At Power-On Reset, transients may cause the LCPLL to lock onto a
clock that is momentarily unstable. This is normally seen in QSGMII
setups where the higher speed 6G SerDes is being used.
This patch adds an initial LCPLL Reset to the PHY (first instance)
to avoid this issue.

Fixes: e4f9ba642f ("net: phy: mscc: add support for VSC8514 PHY.")
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-16 14:06:18 -08:00
..
Makefile net: phy: mscc: 1588 block initialization 2020-06-24 14:33:16 -07:00
mscc_fc_buffer.h net: phy: mscc: fix copyright and author information in MACsec 2020-06-24 14:33:16 -07:00
mscc_mac.h net: phy: mscc: fix copyright and author information in MACsec 2020-06-24 14:33:16 -07:00
mscc_macsec.c net: phy: mscc: remove non-MACSec compatible phy 2020-11-13 15:08:07 -08:00
mscc_macsec.h net: phy: mscc: fix copyright and author information in MACsec 2020-06-24 14:33:16 -07:00
mscc_main.c net: phy: mscc: adding LCPLL reset to VSC8514 2021-02-16 14:06:18 -08:00
mscc_ptp.c net: phy: mscc: use new PTP_MSGTYPE_* defines 2020-11-25 12:23:21 -08:00
mscc_ptp.h net: phy: mscc: use new PTP_MSGTYPE_* defines 2020-11-25 12:23:21 -08:00
mscc.h net: phy: mscc: adding LCPLL reset to VSC8514 2021-02-16 14:06:18 -08:00