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3cc624beba
linux/drivers/fpga
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Ivan Bornyakov 3cc624beba
fpga: fpga-mgr: support bitstream offset in image buffer 
At the moment FPGA manager core loads to the device entire image
provided to fpga_mgr_load(). But it is not always whole FPGA image
buffer meant to be written to the device. In particular, .dat formatted
image for Microchip MPF contains meta info in the header that is not
meant to be written to the device. This is issue for those low level
drivers that loads data to the device with write() fpga_manager_ops
callback, since write() can be called in iterator over scatter-gather
table, not only linear image buffer. On the other hand, write_sg()
callback is provided with whole image in scatter-gather form and can
decide itself which part should be sent to the device.

Add header_size and data_size to the fpga_image_info struct, add
skip_header to the fpga_manager_ops struct and adjust fpga_mgr_write()
callers with respect to them.

  * info->header_size indicates part at the beginning of image buffer
    that contains some meta info. It is optional and can be 0,
    initialized with mops->initial_header_size.

  * mops->skip_header tells fpga-mgr core whether write should start
    from the beginning of image buffer or at the offset of header_size.

  * info->data_size is the size of bitstream data that is meant to be
    written to the device. It is also optional and can be 0, which
    means bitstream data is up to the end of image buffer.

Also add parse_header() callback to fpga_manager_ops, which purpose is
to set info->header_size and info->data_size. At least
initial_header_size bytes of image buffer will be passed into
parse_header() first time. If it is not enough, parse_header() should
set desired size into info->header_size and return -EAGAIN, then it will
be called again with greater part of image buffer on the input.

Suggested-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
Acked-by: Xu Yilun <yilun.xu@intel.com>
Link: https://lore.kernel.org/r/20220623163248.3672-2-i.bornyakov@metrotek.ru
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
2022-06-24 12:11:18 +08:00
..
altera-cvp.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
altera-fpga2sdram.c fpga: bridge: Use standard dev_release for class driver 2021-11-28 14:02:13 -08:00
altera-freeze-bridge.c fpga: bridge: Use standard dev_release for class driver 2021-11-28 14:02:13 -08:00
altera-hps2fpga.c fpga: bridge: Use standard dev_release for class driver 2021-11-28 14:02:13 -08:00
altera-pr-ip-core-plat.c fpga: fpga-mgr: altera-pr-ip: Simplify registration 2020-12-01 18:49:32 +01:00
altera-pr-ip-core.c fpga: altera-pr-ip: fix unsigned comparison with less than zero 2022-06-10 15:48:23 +08:00
altera-ps-spi.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
dfl-afu-dma-region.c fpga: dfl: afu: convert get_user_pages() --> pin_user_pages() 2020-06-18 18:12:06 -07:00
dfl-afu-error.c fpga: dfl: afu: harden port enable logic 2021-03-24 11:15:04 -07:00
dfl-afu-main.c fpga: dfl: afu: harden port enable logic 2021-03-24 11:15:04 -07:00
dfl-afu-region.c
dfl-afu.h fpga: dfl: afu: harden port enable logic 2021-03-24 11:15:04 -07:00
dfl-fme-br.c fpga: bridge: Use standard dev_release for class driver 2021-11-28 14:02:13 -08:00
dfl-fme-error.c fpga: dfl: fme: add interrupt support for global error reporting 2020-07-06 21:35:42 -07:00
dfl-fme-main.c fpga: dfl: fme: add interrupt support for global error reporting 2020-07-06 21:35:42 -07:00
dfl-fme-mgr.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
dfl-fme-perf.c fpga: dfl: fme: Fix cpu hotplug issue in performance reporting 2021-07-27 11:05:16 -07:00
dfl-fme-pr.c fpga: fix spelling mistakes 2021-07-21 19:54:21 -07:00
dfl-fme-pr.h
dfl-fme-region.c fpga: region: Use standard dev_release for class driver 2021-11-28 14:02:41 -08:00
dfl-fme.h fpga: dfl: fme: add performance reporting support 2020-04-28 15:49:28 +02:00
dfl-n3000-nios.c fpga: fix spelling mistakes 2021-07-21 19:54:21 -07:00
dfl-pci.c fpga: dfl: Allow Port to be linked to FME's DFL 2022-05-10 16:05:38 +08:00
dfl.c fpga: Directly use ida_alloc()/free() 2022-06-08 17:04:39 +08:00
dfl.h fpga: dfl: Allow Port to be linked to FME's DFL 2022-05-10 16:05:38 +08:00
fpga-bridge.c fpga: Directly use ida_alloc()/free() 2022-06-08 17:04:39 +08:00
fpga-mgr.c fpga: fpga-mgr: support bitstream offset in image buffer 2022-06-24 12:11:18 +08:00
fpga-region.c fpga: Directly use ida_alloc()/free() 2022-06-08 17:04:39 +08:00
ice40-spi.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
intel-m10-bmc-sec-update.c fpga: m10bmc-sec: add max10 secure update functions 2022-06-08 17:04:39 +08:00
Kconfig fpga: m10bmc-sec: create max10 bmc secure update 2022-06-08 17:04:37 +08:00
machxo2-spi.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
Makefile fpga: m10bmc-sec: create max10 bmc secure update 2022-06-08 17:04:37 +08:00
of-fpga-region.c fpga: fpga-region: fix kernel-doc formatting issues 2022-05-10 16:05:00 +08:00
socfpga-a10.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
socfpga.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
stratix10-soc.c fpga: stratix10-soc: Do not use ret uninitialized in s10_probe() 2021-12-02 20:07:17 -08:00
ts73xx-fpga.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
versal-fpga.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
xilinx-pr-decoupler.c fpga: bridge: Use standard dev_release for class driver 2021-11-28 14:02:13 -08:00
xilinx-spi.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
zynq-fpga.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00
zynqmp-fpga.c fpga: mgr: Use standard dev_release for class driver 2021-11-28 13:59:13 -08:00