3071f13d75
This adds a new dynamic PMU to the Perf Events framework to program and control the L3 cache PMUs in some Qualcomm Technologies SOCs. The driver supports a distributed cache architecture where the overall cache for a socket is comprised of multiple slices each with its own PMU. Access to each individual PMU is provided even though all CPUs share all the slices. User space needs to aggregate to individual counts to provide a global picture. The driver exports formatting and event information to sysfs so it can be used by the perf user space tools with the syntaxes: perf stat -a -e l3cache_0_0/read-miss/ perf stat -a -e l3cache_0_0/event=0x21/ Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org> [will: fixed sparse issues] Signed-off-by: Will Deacon <will.deacon@arm.com>
42 lines
1.1 KiB
Plaintext
42 lines
1.1 KiB
Plaintext
#
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# Performance Monitor Drivers
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#
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menu "Performance monitor support"
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config ARM_PMU
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depends on PERF_EVENTS && (ARM || ARM64)
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bool "ARM PMU framework"
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default y
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help
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Say y if you want to use CPU performance monitors on ARM-based
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systems.
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config QCOM_L2_PMU
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bool "Qualcomm Technologies L2-cache PMU"
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depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI
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help
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Provides support for the L2 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L2 cache PMU into the perf events subsystem for
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monitoring L2 cache events.
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config QCOM_L3_PMU
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bool "Qualcomm Technologies L3-cache PMU"
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depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI
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select QCOM_IRQ_COMBINER
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help
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Provides support for the L3 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L3 cache PMU into the perf events subsystem for
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monitoring L3 cache events.
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config XGENE_PMU
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depends on PERF_EVENTS && ARCH_XGENE
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bool "APM X-Gene SoC PMU"
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default n
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help
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Say y if you want to use APM X-Gene SoC performance monitors.
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endmenu
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