3d21a46093
json-schema versions draft7 and earlier have a weird behavior in that any keywords combined with a '$ref' are ignored (silently). The correct form was to put a '$ref' under an 'allOf'. This behavior is now changed in the 2019-09 json-schema spec and '$ref' can be mixed with other keywords. The json-schema library doesn't yet support this, but the tooling now does a fixup for this and either way works. This has been a constant source of review comments, so let's change this treewide so everyone copies the simpler syntax. Scripted with ruamel.yaml with some manual fixups. Some minor whitespace changes from the script. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-By: Vinod Koul <vkoul@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Wolfram Sang <wsa@the-dreams.de> # for I2C Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio Reviewed-by: Stephen Boyd <sboyd@kernel.org> # clock Signed-off-by: Rob Herring <robh@kernel.org>
153 lines
4.5 KiB
YAML
153 lines
4.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra124 SoC Memory Controller
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maintainers:
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |
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Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
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These are interleaved to provide high performance with the load shared across
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two memory channels. The Tegra124 Memory Controller handles memory requests
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from internal clients and arbitrates among them to allocate memory bandwidth
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for DDR3L and LPDDR3 SDRAMs.
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properties:
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compatible:
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const: nvidia,tegra124-mc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: mc
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interrupts:
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maxItems: 1
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"#reset-cells":
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const: 1
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"#iommu-cells":
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const: 1
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patternProperties:
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"^emc-timings-[0-9]+$":
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type: object
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properties:
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nvidia,ram-code:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Value of RAM_CODE this timing set is used for.
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patternProperties:
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"^timing-[0-9]+$":
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type: object
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properties:
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clock-frequency:
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description:
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Memory clock rate in Hz.
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minimum: 1000000
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maximum: 1066000000
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nvidia,emem-configuration:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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Values to be written to the EMEM register block. See section
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"15.6.1 MC Registers" in the TRM.
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items:
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- description: MC_EMEM_ARB_CFG
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- description: MC_EMEM_ARB_OUTSTANDING_REQ
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- description: MC_EMEM_ARB_TIMING_RCD
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- description: MC_EMEM_ARB_TIMING_RP
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- description: MC_EMEM_ARB_TIMING_RC
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- description: MC_EMEM_ARB_TIMING_RAS
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- description: MC_EMEM_ARB_TIMING_FAW
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- description: MC_EMEM_ARB_TIMING_RRD
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- description: MC_EMEM_ARB_TIMING_RAP2PRE
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- description: MC_EMEM_ARB_TIMING_WAP2PRE
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- description: MC_EMEM_ARB_TIMING_R2R
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- description: MC_EMEM_ARB_TIMING_W2W
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- description: MC_EMEM_ARB_TIMING_R2W
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- description: MC_EMEM_ARB_TIMING_W2R
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- description: MC_EMEM_ARB_DA_TURNS
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- description: MC_EMEM_ARB_DA_COVERS
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- description: MC_EMEM_ARB_MISC0
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- description: MC_EMEM_ARB_MISC1
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- description: MC_EMEM_ARB_RING1_THROTTLE
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required:
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- clock-frequency
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- nvidia,emem-configuration
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additionalProperties: false
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required:
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- nvidia,ram-code
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- "#reset-cells"
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- "#iommu-cells"
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additionalProperties: false
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examples:
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- |
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memory-controller@70019000 {
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compatible = "nvidia,tegra124-mc";
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reg = <0x0 0x70019000 0x0 0x1000>;
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clocks = <&tegra_car 32>;
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clock-names = "mc";
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interrupts = <0 77 4>;
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#iommu-cells = <1>;
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#reset-cells = <1>;
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emc-timings-3 {
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nvidia,ram-code = <3>;
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timing-12750000 {
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clock-frequency = <12750000>;
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nvidia,emem-configuration = <
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0x40040001 /* MC_EMEM_ARB_CFG */
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0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
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0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
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0x00000001 /* MC_EMEM_ARB_TIMING_RP */
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0x00000002 /* MC_EMEM_ARB_TIMING_RC */
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0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
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0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
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0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
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0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
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0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
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0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
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0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
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0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
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0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
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0x06030203 /* MC_EMEM_ARB_DA_TURNS */
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0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
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0x77e30303 /* MC_EMEM_ARB_MISC0 */
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0x70000f03 /* MC_EMEM_ARB_MISC1 */
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0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
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>;
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};
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};
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};
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