Wei Yongjun bb8727096c clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static ...

Fixes the following sparse warning:

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c:244:18: warning:
 symbol 'tegra210_cpu_cvb_tables' was not declared. Should it be static?

Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

2019-02-18 11:16:22 +01:00

..

clk-audio-sync.c

clk: tegra: Fix maximum audio sync clock for Tegra124/210

2018-12-14 13:32:55 -08:00

clk-bpmp.c

clk: tegra: bpmp: Don't crash when a clock fails to register

2018-07-08 16:56:24 -07:00

clk-dfll.c

clk: tegra: dfll: round down voltages based on alignment

2019-02-06 14:29:08 +01:00

clk-dfll.h

clk: tegra: dfll: CVB calculation alignment with the regulator

2019-02-06 14:28:41 +01:00

clk-divider.c

Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next

2018-08-14 22:58:53 -07:00

clk-emc.c

clk: tegra: emc: Avoid out-of-bounds bug

2018-07-08 17:10:19 -07:00

clk-id.h

clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

2018-07-25 14:26:22 -07:00

clk-periph-fixed.c

clk: tegra: Add fixed factor peripheral clock type

2016-04-28 12:41:47 +02:00

clk-periph-gate.c

clk: tegra: Fix disable unused for clocks sharing enable bit

2017-03-20 14:13:52 +01:00

clk-periph.c

clk: tegra: Add peripheral clock registration helper

2017-10-19 16:38:40 +02:00

clk-pll-out.c

clk: tegra: Properly include clk.h

2015-07-20 11:11:17 -07:00

clk-pll.c

clk: tegra: Return the exact clock rate from clk_round_rate

2018-12-14 13:32:55 -08:00

clk-sdmmc-mux.c

clk: tegra: Add sdmmc mux divider clock

2018-07-25 13:45:09 -07:00

clk-super.c

clk: tegra: Add super clock mux/divider

2017-03-20 14:07:33 +01:00

clk-tegra20.c

clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC

2018-11-08 12:47:18 +01:00

clk-tegra30.c

clk: tegra30: Use Tegra CPU powergate helper function

2018-12-14 13:32:55 -08:00

clk-tegra114.c

clk: tegra: Fix maximum audio sync clock for Tegra124/210

2018-12-14 13:32:55 -08:00

clk-tegra124-dfll-fcpu.c

clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static

2019-02-18 11:16:22 +01:00

clk-tegra124.c

clk: tegra: Fix maximum audio sync clock for Tegra124/210

2018-12-14 13:32:55 -08:00

clk-tegra210.c

clk: tegra: Fix maximum audio sync clock for Tegra124/210

2018-12-14 13:32:55 -08:00

clk-tegra-audio.c

clk: tegra: Fix maximum audio sync clock for Tegra124/210

2018-12-14 13:32:55 -08:00

clk-tegra-fixed.c

clk: tegra: Remove trailing blank line

2016-04-28 12:41:45 +02:00

clk-tegra-periph.c

clk: tegra: get rid of duplicate defines

2018-12-14 13:32:54 -08:00

clk-tegra-pmc.c

clk: tegra: Propagate clk_out_x rate to parent

2017-04-04 16:00:28 +02:00

clk-tegra-super-gen4.c

clk: tegra: Mark HCLK, SCLK and EMC as critical

2018-03-12 13:58:58 +01:00

clk-utils.c

clk: tegra: Refactor fractional divider calculation

2018-07-25 13:43:34 -07:00

clk.c

treewide: kzalloc() -> kcalloc()

2018-06-12 16:19:22 -07:00

clk.h

clk: tegra: Fix maximum audio sync clock for Tegra124/210

2018-12-14 13:32:55 -08:00

cvb.c

clk: tegra: dfll: CVB calculation alignment with the regulator

2019-02-06 14:28:41 +01:00

cvb.h

clk: tegra: dfll: add CVB tables for Tegra210

2019-02-06 14:29:23 +01:00

Kconfig

clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210

2019-02-06 14:29:37 +01:00

Makefile

clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210

2019-02-06 14:29:37 +01:00