Geert Uytterhoeven 3d5155eaad clk: renesas: r8a7795: Add CR clock
Add the CR core clock, which is used by the Secure Engine (SCEG).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Gilad Ben-Yossef <gilad@benyossef.com>
2018-06-19 10:19:51 +02:00
..
2018-06-12 16:19:22 -07:00
2018-06-12 16:19:22 -07:00
2018-06-12 16:19:22 -07:00