Peter De Schrijver 3dd065e70e clk: tegra: change post IDDQ release delay to 5us
Increase delay after PLL IDDQ release to 5us per PLL specifications.

based on work by Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-23 15:59:42 -07:00
..
2017-02-03 12:36:36 -08:00
2016-04-28 10:52:28 +02:00
2017-03-20 14:06:23 +01:00
2017-03-20 14:06:23 +01:00
2017-03-20 14:06:23 +01:00
2017-02-03 12:36:36 -08:00
2017-02-03 12:36:36 -08:00