Chen-Yu Tsai 3de64bf187 clk: sunxi-ng: Support separately grouped PLL lock status register ...

On the Allwinner A80 SoC, the PLL lock status indicators are grouped
together in a separate register, as opposed to being scattered in each
PLL's configuration register.

Add a flag to support this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

2017-01-30 08:36:20 +01:00

..

ccu_common.c

clk: sunxi-ng: Support separately grouped PLL lock status register

2017-01-30 08:36:20 +01:00

ccu_common.h

clk: sunxi-ng: Support separately grouped PLL lock status register

2017-01-30 08:36:20 +01:00

ccu_div.c

clk: sunxi-ng: Call divider_round_rate if we only have a single parent

2017-01-27 11:05:34 +01:00

ccu_div.h

clk: sunxi-ng: Implement factors offsets

2017-01-23 11:44:27 +01:00

ccu_frac.c

clk: sunxi-ng: Rename the internal structures

2016-10-20 19:24:20 +02:00

ccu_frac.h

clk: sunxi-ng: Rename the internal structures

2016-10-20 19:24:20 +02:00

ccu_gate.c

clk: sunxi-ng: Add gate clock support

2016-07-08 18:04:38 -07:00

ccu_gate.h

clk: sunxi-ng: Add gate clock support

2016-07-08 18:04:38 -07:00

ccu_mp.c

clk: sunxi-ng: Implement factors offsets

2017-01-23 11:44:27 +01:00

ccu_mp.h

clk: sunxi-ng: Rename the internal structures

2016-10-20 19:24:20 +02:00

ccu_mult.c

clk: sunxi-ng: Implement multiplier maximum

2017-01-23 11:45:01 +01:00

ccu_mult.h

clk: sunxi-ng: Implement multiplier maximum

2017-01-23 11:45:01 +01:00

ccu_mux.c

clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT

2017-01-30 08:36:03 +01:00

ccu_mux.h

clk: sunxi-ng: mux: Add mux table macro

2016-09-10 11:41:18 +02:00

ccu_nk.c

clk: sunxi-ng: Implement multiplier maximum

2017-01-23 11:45:01 +01:00

ccu_nk.h

clk: sunxi-ng: Rename the internal structures

2016-10-20 19:24:20 +02:00

ccu_nkm.c

clk: sunxi-ng: Implement multiplier maximum

2017-01-23 11:45:01 +01:00

ccu_nkm.h

clk: sunxi-ng: Rename the internal structures

2016-10-20 19:24:20 +02:00

ccu_nkmp.c

clk: sunxi-ng: Implement multiplier maximum

2017-01-23 11:45:01 +01:00

ccu_nkmp.h

clk: sunxi-ng: Rename the internal structures

2016-10-20 19:24:20 +02:00

ccu_nm.c

clk: sunxi-ng: Implement multiplier maximum

2017-01-23 11:45:01 +01:00

ccu_nm.h

clk: sunxi-ng: Rename the internal structures

2016-10-20 19:24:20 +02:00

ccu_phase.c

clk: sunxi-ng: Add phase clock support

2016-07-08 18:04:45 -07:00

ccu_phase.h

clk: sunxi-ng: Add phase clock support

2016-07-08 18:04:45 -07:00

ccu_reset.c

…

ccu_reset.h

…

ccu-sun5i.c

clk: sunxi-ng: Add sun5i CCU driver

2017-01-23 11:45:29 +01:00

ccu-sun5i.h

clk: sunxi-ng: Add sun5i CCU driver

2017-01-23 11:45:29 +01:00

ccu-sun6i-a31.c

clk: sunxi-ng: A31: Fix spdif clock register

2017-01-02 22:24:55 +01:00

ccu-sun6i-a31.h

clk: sunxi-ng: Add A31/A31s clocks

2016-08-25 22:31:43 +02:00

ccu-sun8i-a23-a33.h

clk: sunxi-ng: Add A33 CCU support

2016-09-10 11:41:19 +02:00

ccu-sun8i-a23.c

clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks

2016-11-11 21:47:36 +01:00

ccu-sun8i-a33.c

clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU

2017-01-27 11:05:57 +01:00

ccu-sun8i-h3.c

clk: sunxi-ng: fix PLL_CPUX adjusting on H3

2017-01-02 22:24:55 +01:00

ccu-sun8i-h3.h

clk: sunxi-ng: Add H3 clocks

2016-07-08 18:05:12 -07:00

ccu-sun8i-v3s.c

clk: sunxi-ng: add support for V3s CCU

2017-01-20 21:39:03 +01:00

ccu-sun8i-v3s.h

clk: sunxi-ng: add support for V3s CCU

2017-01-20 21:39:03 +01:00

ccu-sun50i-a64.c

clk: sunxi-ng: Mark structs static and cleanup spaces

2016-11-16 11:27:28 -08:00

ccu-sun50i-a64.h

clk: sunxi-ng: Add A64 clocks

2016-11-03 09:06:18 +01:00

Kconfig

clk: sunxi-ng: Add sun5i CCU driver

2017-01-23 11:45:29 +01:00

Makefile

clk: sunxi-ng: Add sun5i CCU driver

2017-01-23 11:45:29 +01:00