81fe00fa4e
The CMA reserved memory nodes have been added for both the IPUs and the DSP1 remoteproc devices on the DRA72 EVM rev C board, and assigned to the respective rproc device nodes. These match the configuration used on the DRA72 EVM board. Both the CMA nodes and the corresponding rproc nodes are also enabled to enable these processors on the DRA72 EVM rev C board. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
158 lines
3.4 KiB
Plaintext
158 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "dra72-evm-common.dtsi"
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#include "dra72x-mmc-iodelay.dtsi"
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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model = "TI DRA722 Rev C EVM";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ipu2_cma_pool: ipu2_cma@95800000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x95800000 0x0 0x3800000>;
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reusable;
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status = "okay";
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};
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dsp1_cma_pool: dsp1_cma@99000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x99000000 0x0 0x4000000>;
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reusable;
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status = "okay";
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};
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ipu1_cma_pool: ipu1_cma@9d000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x9d000000 0x0 0x2000000>;
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reusable;
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status = "okay";
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};
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};
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evm_1v8_sw: fixedregulator-evm_1v8 {
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compatible = "regulator-fixed";
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regulator-name = "evm_1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&smps4_reg>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&i2c1 {
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tps65917: tps65917@58 {
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reg = <0x58>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
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};
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};
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#include "dra72-evm-tps65917.dtsi"
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&ldo2_reg {
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/* LDO2_OUT --> VDDA_1V8_PHY2 */
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regulator-always-on;
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regulator-boot-on;
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};
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&hdmi {
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vdda-supply = <&ldo2_reg>;
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};
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&pcf_gpio_21 {
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interrupt-parent = <&gpio3>;
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interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
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};
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&mac {
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mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
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<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
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<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
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dual_emac;
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};
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&cpsw_emac0 {
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phy-handle = <&dp83867_0>;
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phy-mode = "rgmii-id";
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dual_emac_res_vlan = <1>;
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};
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&cpsw_emac1 {
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phy-handle = <&dp83867_1>;
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phy-mode = "rgmii-id";
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dual_emac_res_vlan = <2>;
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};
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&davinci_mdio {
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dp83867_0: ethernet-phy@2 {
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reg = <2>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,min-output-impedance;
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interrupt-parent = <&gpio6>;
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interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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dp83867_1: ethernet-phy@3 {
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reg = <3>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,min-output-impedance;
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interrupt-parent = <&gpio6>;
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interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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&mmc1 {
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pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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pinctrl-0 = <&mmc1_pins_default>;
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pinctrl-1 = <&mmc1_pins_hs>;
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pinctrl-2 = <&mmc1_pins_sdr12>;
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pinctrl-3 = <&mmc1_pins_sdr25>;
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pinctrl-4 = <&mmc1_pins_sdr50>;
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pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
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pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
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vqmmc-supply = <&ldo1_reg>;
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};
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&mmc2 {
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pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
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pinctrl-0 = <&mmc2_pins_default>;
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pinctrl-1 = <&mmc2_pins_hs>;
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pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
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pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
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vmmc-supply = <&evm_1v8_sw>;
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};
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&ipu2 {
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status = "okay";
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memory-region = <&ipu2_cma_pool>;
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};
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&ipu1 {
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status = "okay";
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memory-region = <&ipu1_cma_pool>;
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};
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&dsp1 {
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status = "okay";
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memory-region = <&dsp1_cma_pool>;
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};
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