b0d0bb1b6f
Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs. These SoCs have very similar memory maps and this will avoid duplicating nodes across multiple dtsis. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
84 lines
1.8 KiB
Plaintext
84 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2020 thingy.jp.
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* Author: Daniel Palmer <daniel@thingy.jp>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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};
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arch_timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
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| IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
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| IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
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| IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
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| IRQ_TYPE_LEVEL_LOW)>;
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/*
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* we shouldn't need this but the vendor
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* u-boot is broken
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*/
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clock-frequency = <6000000>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x16001000 0x16001000 0x00007000>,
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<0x1f000000 0x1f000000 0x00400000>;
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gic: interrupt-controller@16001000 {
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compatible = "arm,cortex-a7-gic";
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reg = <0x16001000 0x1000>,
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<0x16002000 0x2000>,
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<0x16004000 0x2000>,
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<0x16006000 0x2000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
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| IRQ_TYPE_LEVEL_LOW)>;
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};
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riu: bus@1f000000 {
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compatible = "simple-bus";
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reg = <0x1f000000 0x00400000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1f000000 0x00400000>;
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l3bridge: l3bridge@204400 {
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compatible = "mstar,l3bridge";
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reg = <0x204400 0x200>;
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};
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pm_uart: uart@221000 {
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compatible = "ns16550a";
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reg = <0x221000 0x100>;
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reg-shift = <3>;
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clock-frequency = <172000000>;
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status = "disabled";
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};
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};
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};
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};
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