8adea9b945
Add binding documentation for topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys on MT8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200918132303.2831815-1-fparent@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
Mediatek infracfg controller
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============================
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The Mediatek infracfg controller provides various clocks and reset
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outputs to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt2712-infracfg", "syscon"
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- "mediatek,mt6765-infracfg", "syscon"
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- "mediatek,mt6779-infracfg_ao", "syscon"
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- "mediatek,mt6797-infracfg", "syscon"
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- "mediatek,mt7622-infracfg", "syscon"
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- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt7629-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8167-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- "mediatek,mt8183-infracfg", "syscon"
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- "mediatek,mt8516-infracfg", "syscon"
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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The infracfg controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Also it uses the common reset controller binding from
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Documentation/devicetree/bindings/reset/reset.txt.
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The available reset outputs are defined in
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dt-bindings/reset/mt*-resets.h
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Example:
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infracfg: power-controller@10001000 {
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compatible = "mediatek,mt8173-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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