754e9883d4
Clock gating setting is still performed even when the corresponding CG feature is not supported. And the tricky part is disablement is actually performed no matter for enablement or disablement request. That seems not logically right. Considering HW should already properly take care of the CG state, we will just skip the corresponding clock gating setting when the feature is not supported. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "athub_v2_0.h"
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#include "athub/athub_2_0_0_offset.h"
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#include "athub/athub_2_0_0_sh_mask.h"
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#include "athub/athub_2_0_0_default.h"
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#include "soc15_common.h"
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static void
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athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
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return;
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def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
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if (enable)
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data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
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else
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data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
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if (def != data)
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WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
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}
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static void
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athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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if (!((adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
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(adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)))
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return;
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def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
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if (enable)
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data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
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else
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data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
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if (def != data)
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WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
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}
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int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
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enum amd_clockgating_state state)
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{
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if (amdgpu_sriov_vf(adev))
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return 0;
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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case CHIP_NAVI12:
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athub_v2_0_update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
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athub_v2_0_update_medium_grain_light_sleep(adev,
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state == AMD_CG_STATE_GATE);
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break;
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default:
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break;
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}
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return 0;
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}
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void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
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{
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int data;
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/* AMD_CG_SUPPORT_ATHUB_MGCG */
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data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
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if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
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/* AMD_CG_SUPPORT_ATHUB_LS */
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if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_ATHUB_LS;
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}
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