754e9883d4
Clock gating setting is still performed even when the corresponding CG feature is not supported. And the tricky part is disablement is actually performed no matter for enablement or disablement request. That seems not logically right. Considering HW should already properly take care of the CG state, we will just skip the corresponding clock gating setting when the feature is not supported. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
81 lines
2.7 KiB
C
81 lines
2.7 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "smuio_v11_0.h"
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#include "smuio/smuio_11_0_0_offset.h"
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#include "smuio/smuio_11_0_0_sh_mask.h"
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static u32 smuio_v11_0_get_rom_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
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}
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static u32 smuio_v11_0_get_rom_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
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}
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static void smuio_v11_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
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{
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u32 def, data;
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/* enable/disable ROM CG is not supported on APU */
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if (adev->flags & AMD_IS_APU)
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return;
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if (!(adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
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return;
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def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
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if (enable)
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data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
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CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
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else
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data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
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CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
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if (def != data)
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WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data);
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}
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static void smuio_v11_0_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags)
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{
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u32 data;
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/* CGTT_ROM_CLK_CTRL0 is not available for APU */
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if (adev->flags & AMD_IS_APU)
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return;
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data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
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if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
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*flags |= AMD_CG_SUPPORT_ROM_MGCG;
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}
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const struct amdgpu_smuio_funcs smuio_v11_0_funcs = {
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.get_rom_index_offset = smuio_v11_0_get_rom_index_offset,
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.get_rom_data_offset = smuio_v11_0_get_rom_data_offset,
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.update_rom_clock_gating = smuio_v11_0_update_rom_clock_gating,
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.get_clock_gating_state = smuio_v11_0_get_clock_gating_state,
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};
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