41195d236e
ARC common code to enable a SMP system + ISS provided SMP extensions. ARC700 natively lacks SMP support, hence some of the core features are are only enabled if SoCs have the necessary h/w pixie-dust. This includes: -Inter Processor Interrupts (IPI) -Cache coherency -load-locked/store-conditional ... The low level exception handling would be completely broken in SMP because we don't have hardware assisted stack switching. Thus a fair bit of this code is repurposing the MMU_SCRATCH reg for event handler prologues to keep them re-entrant. Many thanks to Rajeshwar Ranga for his initial "major" contributions to SMP Port (back in 2008), and to Noam Camus and Gilad Ben-Yossef for help with resurrecting that in 3.2 kernel (2012). Note that this platform code is again singleton design pattern - so multiple SMP platforms won't build at the moment - this deficiency is addressed in subsequent patches within this series. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rajeshwar Ranga <rajeshwar.ranga@gmail.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Gilad Ben-Yossef <gilad@benyossef.com>
142 lines
4.2 KiB
C
142 lines
4.2 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARC_SMP_H
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#define __ASM_ARC_SMP_H
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#ifdef CONFIG_SMP
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/threads.h>
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#define raw_smp_processor_id() (current_thread_info()->cpu)
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/* including cpumask.h leads to cyclic deps hence this Forward declaration */
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struct cpumask;
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/*
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* APIs provided by arch SMP code to generic code
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*/
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extern void arch_send_call_function_single_ipi(int cpu);
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extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
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/*
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* APIs provided by arch SMP code to rest of arch code
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*/
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extern void __init smp_init_cpus(void);
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extern void __init first_lines_of_secondary(void);
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/*
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* API expected BY platform smp code (FROM arch smp code)
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*
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* smp_ipi_irq_setup:
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* Takes @cpu and @irq to which the arch-common ISR is hooked up
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*/
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extern int smp_ipi_irq_setup(int cpu, int irq);
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/*
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* APIs expected FROM platform smp code
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*
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* arc_platform_smp_cpuinfo:
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* returns a string containing info for /proc/cpuinfo
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*
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* arc_platform_smp_init_cpu:
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* Called from start_kernel_secondary to do any CPU local setup
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* such as starting a timer, setting up IPI etc
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*
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* arc_platform_smp_wait_to_boot:
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* Called from early bootup code for non-Master CPUs to "park" them
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*
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* arc_platform_smp_wakeup_cpu:
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* Called from __cpu_up (Master CPU) to kick start another one
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*
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* arc_platform_ipi_send:
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* Takes @cpumask to which IPI(s) would be sent.
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* The actual msg-id/buffer is manager in arch-common code
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*
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* arc_platform_ipi_clear:
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* Takes @cpu which got IPI at @irq to do any IPI clearing
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*/
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extern const char *arc_platform_smp_cpuinfo(void);
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extern void arc_platform_smp_init_cpu(void);
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extern void arc_platform_smp_wait_to_boot(int cpu);
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extern void arc_platform_smp_wakeup_cpu(int cpu, unsigned long pc);
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extern void arc_platform_ipi_send(const struct cpumask *callmap);
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extern void arc_platform_ipi_clear(int cpu, int irq);
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#endif /* CONFIG_SMP */
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/*
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* ARC700 doesn't support atomic Read-Modify-Write ops.
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* Originally Interrupts had to be disabled around code to gaurantee atomicity.
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* The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
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* based on retry-if-irq-in-atomic (with hardware assist).
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* However despite these, we provide the IRQ disabling variant
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*
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* (1) These insn were introduced only in 4.10 release. So for older released
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* support needed.
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*
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* (2) In a SMP setup, the LLOCK/SCOND atomiticity across CPUs needs to be
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* gaurantted by the platform (not something which core handles).
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* Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
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* disabling for atomicity.
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*
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* However exported spinlock API is not usable due to cyclic hdr deps
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* (even after system.h disintegration upstream)
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* asm/bitops.h -> linux/spinlock.h -> linux/preempt.h
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* -> linux/thread_info.h -> linux/bitops.h -> asm/bitops.h
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*
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* So the workaround is to use the lowest level arch spinlock API.
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* The exported spinlock API is smart enough to be NOP for !CONFIG_SMP,
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* but same is not true for ARCH backend, hence the need for 2 variants
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*/
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#ifndef CONFIG_ARC_HAS_LLSC
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#include <linux/irqflags.h>
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#ifdef CONFIG_SMP
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#include <asm/spinlock.h>
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extern arch_spinlock_t smp_atomic_ops_lock;
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extern arch_spinlock_t smp_bitops_lock;
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#define atomic_ops_lock(flags) do { \
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local_irq_save(flags); \
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arch_spin_lock(&smp_atomic_ops_lock); \
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} while (0)
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#define atomic_ops_unlock(flags) do { \
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arch_spin_unlock(&smp_atomic_ops_lock); \
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local_irq_restore(flags); \
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} while (0)
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#define bitops_lock(flags) do { \
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local_irq_save(flags); \
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arch_spin_lock(&smp_bitops_lock); \
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} while (0)
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#define bitops_unlock(flags) do { \
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arch_spin_unlock(&smp_bitops_lock); \
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local_irq_restore(flags); \
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} while (0)
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#else /* !CONFIG_SMP */
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#define atomic_ops_lock(flags) local_irq_save(flags)
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#define atomic_ops_unlock(flags) local_irq_restore(flags)
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#define bitops_lock(flags) local_irq_save(flags)
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#define bitops_unlock(flags) local_irq_restore(flags)
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#endif /* !CONFIG_SMP */
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#endif /* !CONFIG_ARC_HAS_LLSC */
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#endif
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