Alex Deucher 41212e2fe7 drm/amdgpu: Fix PCIe lane width calculation
The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and
ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting
value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere.
Port of the radeon fix to amdgpu.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102553
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-04-03 13:08:46 -05:00
..
2018-01-30 18:05:25 +01:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2018-02-06 09:59:40 -08:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2017-12-27 19:00:09 -05:00
2018-03-14 10:59:16 +10:00
2017-11-15 20:42:10 -08:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2018-02-28 15:08:56 -05:00
2018-03-16 15:51:52 -07:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2018-03-28 14:30:41 +10:00
2017-12-19 21:37:24 +10:00
2018-03-28 14:30:41 +10:00
2017-11-15 20:42:10 -08:00
2018-01-25 11:42:25 +10:00
2018-01-24 15:49:04 -05:00