44107d8b7e
Add support for tegra30 SoC. This includes a device tree compatible type for
this SoC ("nvidia,tegra30") and adds L2 cache initialization for this new SoC.
The clock framework is still missing, which prevents most drivers from working.
The basic IRQs are the same, so remove the dependency on
CONFIG_ARCH_TEGRA_2x_SOC.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* arch/arm/mach-tegra/common.c
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/of_irq.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <mach/iomap.h>
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#include <mach/system.h>
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#include "board.h"
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#include "clock.h"
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#include "fuse.h"
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void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
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static const struct of_device_id tegra_dt_irq_match[] __initconst = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
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{ }
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};
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void __init tegra_dt_init_irq(void)
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{
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tegra_init_irq();
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of_irq_init(tegra_dt_irq_match);
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}
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void tegra_assert_system_reset(char mode, const char *cmd)
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{
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void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
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u32 reg;
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reg = readl_relaxed(reset);
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reg |= 0x10;
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writel_relaxed(reg, reset);
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}
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
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/* name parent rate enabled */
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{ "clk_m", NULL, 0, true },
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{ "pll_p", "clk_m", 216000000, true },
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{ "pll_p_out1", "pll_p", 28800000, true },
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{ "pll_p_out2", "pll_p", 48000000, true },
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{ "pll_p_out3", "pll_p", 72000000, true },
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{ "pll_p_out4", "pll_p", 108000000, true },
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{ "sclk", "pll_p_out4", 108000000, true },
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{ "hclk", "sclk", 108000000, true },
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{ "pclk", "hclk", 54000000, true },
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{ "csite", NULL, 0, true },
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{ "emc", NULL, 0, true },
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{ "cpu", NULL, 0, true },
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{ NULL, NULL, 0, 0},
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};
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#endif
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static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
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{
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
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u32 aux_ctrl, cache_type;
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writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
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writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
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cache_type = readl(p + L2X0_CACHE_TYPE);
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aux_ctrl = (cache_type & 0x700) << (17-8);
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aux_ctrl |= 0x6C000001;
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l2x0_init(p, aux_ctrl, 0x8200c3fe);
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#endif
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}
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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void __init tegra20_init_early(void)
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{
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tegra_init_fuse();
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tegra2_init_clocks();
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tegra_clk_init_from_table(tegra20_clk_init_table);
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tegra_init_cache(0x331, 0x441);
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}
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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void __init tegra30_init_early(void)
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{
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tegra_init_cache(0x441, 0x551);
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}
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#endif
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