e79b76e03b
Currently Monitor Mode Control Registers and Sampling registers are part of extended regs. Patch adds support to include Performance Monitor Counter Registers (PMC1 to PMC6 ) as part of extended registers. PMCs are saved in the perf interrupt handler as part of per-cpu array 'pmcs' in struct cpu_hw_events. While capturing the register values for extended regs, fetch these saved PMC values. Simplified the PERF_REG_PMU_MASK_300/31 definition to include PMU SPRs MMCR0 to PMC6. Exclude the unsupported SPRs (MMCR3, SIER2, SIER3) from extended mask value for CPU_FTR_ARCH_300 in the new definition. PERF_REG_EXTENDED_MAX is used to check if any index beyond the extended registers is requested in the sample. Have one PERF_REG_EXTENDED_MAX for CPU_FTR_ARCH_300/CPU_FTR_ARCH_31 since perf_reg_validate function already checks the extended mask for the presence of any unsupported register. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1612335337-1888-3-git-send-email-atrajeev@linux.vnet.ibm.com
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI_ASM_POWERPC_PERF_REGS_H
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#define _UAPI_ASM_POWERPC_PERF_REGS_H
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enum perf_event_powerpc_regs {
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PERF_REG_POWERPC_R0,
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PERF_REG_POWERPC_R1,
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PERF_REG_POWERPC_R2,
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PERF_REG_POWERPC_R3,
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PERF_REG_POWERPC_R4,
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PERF_REG_POWERPC_R5,
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PERF_REG_POWERPC_R6,
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PERF_REG_POWERPC_R7,
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PERF_REG_POWERPC_R8,
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PERF_REG_POWERPC_R9,
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PERF_REG_POWERPC_R10,
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PERF_REG_POWERPC_R11,
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PERF_REG_POWERPC_R12,
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PERF_REG_POWERPC_R13,
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PERF_REG_POWERPC_R14,
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PERF_REG_POWERPC_R15,
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PERF_REG_POWERPC_R16,
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PERF_REG_POWERPC_R17,
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PERF_REG_POWERPC_R18,
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PERF_REG_POWERPC_R19,
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PERF_REG_POWERPC_R20,
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PERF_REG_POWERPC_R21,
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PERF_REG_POWERPC_R22,
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PERF_REG_POWERPC_R23,
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PERF_REG_POWERPC_R24,
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PERF_REG_POWERPC_R25,
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PERF_REG_POWERPC_R26,
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PERF_REG_POWERPC_R27,
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PERF_REG_POWERPC_R28,
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PERF_REG_POWERPC_R29,
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PERF_REG_POWERPC_R30,
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PERF_REG_POWERPC_R31,
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PERF_REG_POWERPC_NIP,
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PERF_REG_POWERPC_MSR,
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PERF_REG_POWERPC_ORIG_R3,
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PERF_REG_POWERPC_CTR,
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PERF_REG_POWERPC_LINK,
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PERF_REG_POWERPC_XER,
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PERF_REG_POWERPC_CCR,
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PERF_REG_POWERPC_SOFTE,
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PERF_REG_POWERPC_TRAP,
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PERF_REG_POWERPC_DAR,
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PERF_REG_POWERPC_DSISR,
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PERF_REG_POWERPC_SIER,
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PERF_REG_POWERPC_MMCRA,
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/* Extended registers */
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PERF_REG_POWERPC_MMCR0,
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PERF_REG_POWERPC_MMCR1,
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PERF_REG_POWERPC_MMCR2,
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PERF_REG_POWERPC_MMCR3,
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PERF_REG_POWERPC_SIER2,
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PERF_REG_POWERPC_SIER3,
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PERF_REG_POWERPC_PMC1,
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PERF_REG_POWERPC_PMC2,
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PERF_REG_POWERPC_PMC3,
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PERF_REG_POWERPC_PMC4,
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PERF_REG_POWERPC_PMC5,
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PERF_REG_POWERPC_PMC6,
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/* Max regs without the extended regs */
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PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
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};
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#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
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/* Exclude MMCR3, SIER2, SIER3 for CPU_FTR_ARCH_300 */
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#define PERF_EXCLUDE_REG_EXT_300 (7ULL << PERF_REG_POWERPC_MMCR3)
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/*
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* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300
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* includes 9 SPRS from MMCR0 to PMC6 excluding the
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* unsupported SPRS in PERF_EXCLUDE_REG_EXT_300.
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*/
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#define PERF_REG_PMU_MASK_300 ((0xfffULL << PERF_REG_POWERPC_MMCR0) - PERF_EXCLUDE_REG_EXT_300)
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/*
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* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31
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* includes 12 SPRs from MMCR0 to PMC6.
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*/
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#define PERF_REG_PMU_MASK_31 (0xfffULL << PERF_REG_POWERPC_MMCR0)
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#define PERF_REG_EXTENDED_MAX (PERF_REG_POWERPC_PMC6 + 1)
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#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
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