Dinh Nguyen f34e8875ae dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi"
The QSPI controller on Intel's SoCFPGA platform does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash.

Introduce the dts compatible "intel,socfpga-qspi" to differentiate the
hardware.

Acked-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: revert to "intel,socfpga-qspi"
v2: change binding to "cdns,qspi-nor-0010" to be more generic for other
    platforms
2021-12-27 04:20:05 -06:00
..
2021-03-27 12:59:03 -06:00