Paul Cercueil 44b06a76ad clk: ingenic/jz4770: Fix incorrect dividers for main clocks ... The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2019-06-07 11:49:00 -07:00
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cgu.c	clk: ingenic: Add support for divider tables	2019-06-07 11:48:58 -07:00
cgu.h	clk: ingenic: Add support for divider tables	2019-06-07 11:48:58 -07:00
jz4725b-cgu.c	clk: ingenic: jz4725b: Add UDC PHY clock	2019-04-11 13:41:11 -07:00
jz4740-cgu.c	clk: ingenic/jz4740: Fix incorrect dividers for main clocks	2019-06-07 11:48:59 -07:00
jz4770-cgu.c	clk: ingenic/jz4770: Fix incorrect dividers for main clocks	2019-06-07 11:49:00 -07:00
jz4780-cgu.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
Kconfig	clk: Add Ingenic jz4725b CGU driver	2018-10-16 15:19:48 -07:00
Makefile	clk: Add Ingenic jz4725b CGU driver	2018-10-16 15:19:48 -07:00